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Add to Calendar2022-11-17 00:00:002022-11-18 00:00:002022 SEMI China Semiconductor Supply Chain International Forum （SEMI China Member Day）Shenzhen ChinaSEMI.org[email protected]America/Los_Angelespublic
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Add to Calendar2022-11-17 00:00:002022-11-18 00:00:002022 SEMI中国半导体供应链国际论坛暨SEMI中国会员日Shenzhen ChinaSEMI.org[email protected]America/Los_Angelespublic
[Northeast Forum 2022] Future Infrastructure—The Impact on the Semiconductor Industry
FUTURE INFRASTRUCTURE—The Impact on the Semiconductor Industry
The SEMI Northeast Forum will bring together industry leaders from the semiconductor supply chain to discuss their vision of the impact of new technologies and applications on the semiconductor industry.
Although we often hear about the end of Moore’s law, expanding markets such as 5G, autonomous vehicles, AI, medical technologies, and improving the energy infrastructure have provided new challenges that foster new innovations. Technologies such as heterogenous integration allowed the industry to migrate from chip scaling to system scaling to address these new applications. These new technologies and applications bring new challenges to the entire ecosystem.
Hear Linx Consulting, Breker, and Teledyne give their insight on:
Heterogeneous Integration
Supply Chain Impact
Verification and Packaging Challenges
Join your colleagues on October 27 to hear industry experts outline a new playbook for innovation that can propel the industry into the next wave of growth.
Teradyne 600 Riverpark Drive North Reading, MA01864 United States
THURSDAY, OCTOBER 27, 2022 | EASTERN TIME
10:00 am
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10:05 am
Northeast Regional Chair
Mark Kahwati
Senior Director of Product Marketing
Teradyne
Welcome
10:05 am
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10:35 am
Mark Thirsk
Managing Partner
Linx Consulting
Supply Chain Impact
10:35 am
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11:05 am
Dave Kelf
Chief Executive Officer
Breker Verification Systems
Changing Product Requirements
11:05 am
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11:35 am
Eric Shoemaker
Director of Marketing, Test Interface Solutions
Teradyne
Future Testing Challenges
11:35 am
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12:05 pm
Christy Tyberg
Sr. Manager, Quantum Hardware Technology Development
IBM
Quantum Computing
12:05 pm
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12:45 pm
Lunch
12:45 pm
Closing Remarks
The SEMI Northeast Chapter Presents—
Future Infrastructure—The Impact on the Semiconductor Industry
SEMI Northeast Forum
In-Person
October 27, 2022 10:00am–1:00pm ET
10:00 am - 1:00 pm
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Add to Calendar2022-10-27 10:00:002022-10-27 13:00:00[Northeast Forum 2022] Future Infrastructure—The Impact on the Semiconductor IndustryThe SEMI Northeast Chapter Presents—Teradyne 600 Riverpark Drive North Reading, MA 01864 United StatesSEMI.org[email protected]America/New_Yorkpublic
America/New_York
Semiconductor technology advancements and added device complexity put ever more stringent requirements on semiconductor manufacturing process monitor and control. Pressure exerted on devices during grinding, CMP, polishing, lamination, bonding, pick and place encapsulation, electrical testing, and packaging can cause failures that may not even be measurable using conventional sensors.
Currently chip test, monitoring and packaging process control is widely done via optical displacement sensors and electrical testing which do not adequately measure the pressure on devices. Without the ability to adequately monitor these processes, root cause failure identification is challenging and maintaining or improving process quality and yield are difficult.
In this webinar the piezoelectric sensor technology will be described and how it used to improve chip test, monitoring and packaging semiconductor processes.
Learn how high-sensitivity, high dynamic range piezo dynamic force measurement sensors can be used to better measure strain during grinding, CMP, polishing, lamination, and electrical test.
MSIG Webinar: Ultra-sensitive, high bandwidth piezoelectric pressure sensors
First in the Innovative Sensors Webinar Series
8:00 am - 9:00 am
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America/Los_Angeles
SiC—Silicon Carbide Webinar #6: Basal Plane Dislocation Defects and the Impact on Device Performance
Silicon carbide (SiC) chips are displacing their incumbent silicon counterparts in several high-volume power applications. As SiC market share continues to grow, the industry is lifting remaining barriers to mass commercialization including the higher-than-silicon chip cost that increases disproportionately with area, defects that limit chip yield and area, reliability and ruggedness concerns, and the need for a trained workforce to skillfully insert SiC into power electronics circuits.
With respect to fabrication, the SiC industry is successfully leveraging the fully depreciated legacy silicon fab infrastructure and is making the relatively small financial investments that allow mature silicon fabs to process SiC. A key aspect of cost-effective fabrication is limiting defects that degrade device performance and compromise yields. Over the past twenty years, significant progress has been made in improving SiC material quality, and Basal-Plane-Dislocations (BPDs) are the last major catastrophic defect. In this presentation, I will discuss how bipolar-current induced electron-hole pair recombination at basal plane dislocations generates stacking fault (SF) formation and expansion, which degrade on-state current conduction. I will present and interpret experimental data of several transistors that exhibit severe BPD related electrical degradation, and of others that demonstrate “intermediate” or no degradation at all. For impacted transistors, I will identify and analyze the electrical characteristics that exhibit degradation as well as those that remain unaffected under bipolar stress. Finally, I will show that BPD related degradation is fully reversed by high temperature annealing, and the transistor returns to its original “undamaged” operational state.
View other webinars in the SiC Series
Webinar #1—Silicon Carbide Material Properties, Key Applications, and Fabrication Basics: Making the Transition from Silicon
Webinar #2—Non-CMOS Compatible SiC Power Device Fabrication in Volume Si Fabs
Webinar #3—Bidirectional SiC and GaN Switch Technology
Webinar #4—Understanding SiC Chip Cost, the Impact of Defects, and the Case of Price Parity with Si at the System Level
