SEMI News

Did you miss the SEMI International Standards Reception at SEMICON West 2018? Not to worry, here are the highlights.SEMI honored two Standards industry leaders for their outstanding accomplishments in developing Standards for the electronics and related industries.Two awards were given recognizing the efforts of each member. The Technical Editor Award recognizes the efforts of a member to ensure the technical excellence of a committee’s Standards. This year’s recipient is Sean Larsen of Lam Research. Mr. Larsen has led the North America EHS Committee and multiple EHS task forces for over a decade. His knowledge of the Regulations, Procedure Manual, and Style Manual, combined with his vast experience in the industry, ensures that complex safety matters are explained in a clear, consistent manner, and ballot authors frequently rely on him for his technical skills in preparing ballots.In addition to co-chairing the North America EHS Committee, Mr. Larsen is currently the co-leader of the SEMI S22 (Electrical Design) Revision TF, the SEMI S2 Non-Ionizing Radiation TF, the SEMI S2 Korean High Pressure Gas Safety TF, and the Control of Hazardous Energy TF.The Corporate Device Member Award recognizes the participation of the user community and is presented to individuals from device manufacturers. This year’s recipient is Don Hadder of Intel. Mr. Hadder has been actively involved in the Standards Program for several years, and currently leads the Chemical Analytical Methods Task Force and chairs the North America Liquid Chemicals Committee. He has successfully re-energized the committee, which is now focused on enabling continued process control improvements for advanced nodes. He recently drove the development of a critical new standard: SEMI C96, Test Method for Determining Density of Chemical Mechanical Polish Slurries, the first document in a series of SEMI Standards that will be devoted specifically to CMP slurry users, IDMs, slurry suppliers, metrology manufacturers and OEM equipment suppliers.Mr. Hadder has worked at Intel for 23 years, where his experience and system ownership has been in Diffusion, Wet Etch, Planar-CMP, Ultra-Pure Water, Waste Treatment Systems, Abatement and Vacuum Systems, Bulk and Specialty Gas, Bulk Chemical Delivery and Planar Chemical Delivery.James Amano, Sr. Dr. International Standards, opened the reception with a few words. He noted that the total number of published SEMI Standards is nearing 1000, and that these documents serve as the backbone of modern day semiconductor manufacturing. SEMI president and CEO Ajit Manocha, speaking at the SEMI International Standards Reception at SEMICON West. Ajit Manocha, President and CEO of SEMI, reminisced how he was an active Standards Member, and how much he got out of SEMI Standards as a young engineer at Bell Labs. He passionately emphasized that SEMI Standards remain critical in this era of new materials and disruptive architectures and processes, calling them the "oxygen of the industry."Laura Nguyen is coordinator, International Standards, at SEMI.

Adapted from the Computer History Museum’s “Celebrating the Birthplace of Silicon Valley” invitation. Work that sowed the seeds of the digital, hyper-connected world we know today all started in a squat, unremarkable building in Mountain View, California. Long before the structure’s foundation was laid, Santa Clara County flourished with orchards, not chips. Between the 1880s and 1940s, eight million fruit trees carpeted Silicon Valley. By 1939, San Jose, with a population of 57,651, was the largest canning and dried-fruit packing center in the world, with 18 canneries, 13 dried-fruit packing houses, and 12 fresh-fruit and vegetable shipping firms*.In 1956, silicon sprouted from new fertile ground.That’s when startup Shockley Semiconductor Laboratory, employing some of the most brilliant young minds in the business, produced Northern California’s first silicon transistor prototypes and formed the technological and cultural bedrock for today’s Silicon Valley.Fed up with William Shockley’s hard-nosed management style, eight Shockley employees – including Gordon Moore, Robert Noyce, Julius Blank, Victor Grinich, Jean Hoerni, Eugene Kleiner, Jay Last, and Sheldon Roberts – resigned in September 1957 and founded Fairchild Semiconductor Corporation. Fairchild was the seedling from which companies valued at over $2 trillion have grown and the source of the integrated circuit “computer chip” that has revolutionized our world.Now, more than 60 years later, the site of Shockley Labs, already an IEEE Historical Milestone, is being formally recognized by the IEEE and the City of Mountain View for its historical significance in a special dedication ceremony on August 15. Thanks to the efforts of many, especially developer Merlone Geier Partners, newly commissioned public sculptures – in the likeness of two early semiconductor devices and a mammoth silicon crystal monument that symbolize the work to come out of the lab – now permanently mark the site, along with various plaques that describe and commemorate the site’s history. The event’s featured speaker is Professor James F. Gibbons, former dean of engineering at Stanford University. Professor Gibbons’ first task at Stanford in 1957 was to work with Shockley and his team to transfer their knowledge of silicon fabrication to Stanford, which could in turn train future engineers for the coming boom in the semiconductor industry. He will share his personal experiences and memories of those early days. Join early semiconductor pioneers, the president of the IEEE, SEMI president and CEO Ajit Manocha and local officials on August 15 to commemorate this legendary Silicon Valley landmark. Guests are invited to enjoy a series of presentations and exhibits and view the stunning sculptures and plaques.The event is free to attend and open to the public. Space is limited so please sign up here to guarantee a seat.Location: 391 San Antonio Road, Palo Alto, California (Phase II of San Antonio Village). Parking is free.*National Park Service, Santa Clara County: California’s Historic Silicon ValleyAriana Raftopoulos is a marketing manager at SEMI.

The march to greater precision, efficiency and safety – the lifeblood of high-technology manufacturing facilities – has taken on a new urgency as emerging applications such artificial intelligence (AI), the Internet of Things (IoT) and Industry 4.0 give new meaning to smart factories. Facing fiercer competition and ever more sophisticated fabrication processes, semiconductor fabs are under intense pressure to keep pace with new technologies as they work to upgrade. Nowhere are the stakes higher than in Taiwan, where high-tech manufacturing contributes mightily to the region’s GDP growth. To help Taiwan fabs confront the challenges and opportunities of designing smarter factories, SEMI and its High-Tech Facility Committee hosted the High-Tech Facility Workshop in June. SEMICON Taiwan 2018 High-Tech Facility Pavilion exhibitors gathered to explore how they can build smarter factories by deploying smart surveillance and disaster prevention technologies along with smart communications systems that better use manufacturing data to drive new safety and product quality efficiencies.During the workshop, SEMI High-Tech Facility Committee representatives shared strides it has made upgrading overseas facilities and developing standards to help establish smart factories in Taiwan.SEMICON Taiwan – 5-7 September at Taipei’s Nangang Exhibition Center – is also an important event for advancing smart manufacturing in Taiwan. Nearly 30 leading global manufacturers will exhibit at the SEMICON Taiwan High-Tech Facility Pavilion. The venue covers operational aspects of semiconductor manufacturing vital to becoming smarter including energy savings, nano-contamination control, facility information modeling, precision instrumentation and control, fire protection, mechatronics, and automation control. The pavilion will also feature a series of theme events offering a comprehensive overview of topics including the latest practices for integrating smart facility capabilities from the perspective of an advanced fab designer.At the TechXPOT stage, High-Tech Facility Pavilion exhibitors will also demonstrate the latest technology breakthroughs and cutting-edge smart factor solutions.The September 6th High-Tech Facility International Forum at SEMICON Taiwan will again gather factory experts and thought leaders from industry and academia to examine “Effective Ways to Make a Facility Smart.“ Experts from industry heavyweights in the fields of wafer foundry, LCD, memory and semiconductor packaging including TSMC, UMC, Innolux, ASE, Micron Taiwan, Winbond and VIS will offer insights into key areas of high-tech facilities including facility electricity, machinery, water management, vaporization and automation systems. On the same day as the forum, the High-Tech Facility Get-Together and High-Tech Facility VIP Dinner will bring together industry elites, academic professionals, and government officials to explore partnership opportunities. SEMI Taiwan and the High-Tech Facility Committee share HTF market trends information, technology updates and standards with SEMI members and exhibitors. Founded in 2013, the High-Tech Facility Committee now has 85 corporate members. Dedicated to accelerating industry collaboration through the integration of Taiwan industrial, government and academic resources, the committee each year holds several group meetings focusing on topics including energy savings, earthquake and fire protection, nano-contamination control, and precision instrumentation and control to advance critical technologies and facilitate standardization. The committee also aims to help the industry become more competitive faster by promoting technology standards that boost productivity and reduce production costs.Please visit semi.huihuidehui.workers.dev and www.semicontaiwan.org for more information about SEMI’s high-tech facility initiatives.Iris Tsou is a marketing specialist at SEMI Taiwan.

Two months after opposing $34 billion in U.S. trade tariffs on behalf of the U.S. semiconductor manufacturing industry, Jonathan Davis, global vice president of industry advocacy at SEMI, this week spoke out against an additional $16 billion in duties on Chinese goods. Testifying before the same U.S. interagency panel mulling the tariffs, Davis called for the removal of 29 tariff lines covering items critical to semiconductor manufacturing including machines and spare parts used to make, wafers, flat panel displays and masks.In his testimony to the panel, Davis stressed that while SEMI supports stronger protections against the theft of valuable intellectual property (IP), tariffs do little to address U.S. concerns over IP loss. Over the past month, SEMI has also submitted written comments and opposed the tariffs in public testimony. The panel includes representatives from the U.S. Trade Representative (USTR), Departments of Treasury, Commerce, State and Defense, and the Council of Economic Advisers.Also testifying, Joe Pon, corporate vice president at Applied Materials, explained that the proposed tariffs will harm small and midsized companies and other U.S. business interests. Describing the tariffs as a tax on exports of high-value U.S. goods, Pon said the duties give non-U.S. firms an unfair competitive advantage.In a parallel push to Davis’s testimony, SEMI, with more than 10 representatives from six member companies, met with 16 congressional offices this week to underscore the damage the tariffs would wreak on the U.S. semiconductor industry. The fallout would include higher operating costs, fewer exports and slower innovation. The tariffs would also curb industry growth and put thousands of high-paying, high-skill jobs at risk. SEMI pressed congressional leaders to reject the tariffs and support a push for congress to re-assert itself on trade policy.Tariffs to Cost U.S. SEMI Members More than $500 MillionSEMI estimates that the second list of proposed tariffs, covering about $16 billion in Chinese goods, will cost its 400 U.S. members more than $500 million annually in additional duties.The tariffs on $34 billion in Chinese goods, which took effect July 6, impact products such as test and inspection equipment as well as spare parts that enter the U.S. from China. That round of tariffs will cost SEMI member companies and estimated tens of millions of dollars annually. SEMI Public Policy Team Asks Members to Review Tariff ListLooking ahead, SEMI encourages members to review the newly released $200 billion tariff list, determine any impact to their businesses and share their findings with SEMI’s public policy team.The U.S. Trade Representative (USTR) has published the exclusion process for products subject to the China 301 tariffs. If your company’s products are subject to tariffs, you can request an exclusion.In evaluating product exclusion requests, the USTR will consider whether a product is available from a source outside of China, whether the additional duties would cause severe economic harm to the requestor or other U.S. interests, and whether the product is strategically important or related to Chinese industrial programs (such as “Made in China 2025”).The deadline for submitting product exclusion requests to USTR is October 9, 2018. Approved exclusions will be effective for one year upon approval and retroactive to July 6, 2018.More information including the process for submitting the product exclusion request can be found here.Any SEMI members with questions should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

The Japan semiconductor manufacturing supply chain is a global semiconductor industry workhorse, producing about one third of world’s chip equipment and more than half of its semiconductor materials. In contributing the vast majority of these products, SEMI Japan member companies hold the high distinction of enabling continuous development of the worldwide semiconductor industry. Aptly, then, technology powerhouses IBM, Nissan Motors and Toshiba offered insights into the latest trends and innovations in computing and smart cars at the late-May SEMI Japan Members Days in Tokyo with 133 technologists from member companies in attendance. As the audience discovered, chip innovation never sleeps and, as futuristic as it can be, invariably gives rise to possibilities beyond the human imagination. That was the message of kickoff presentation “Computing Reimagined – AI/Quantum/IoT” – by Dr. Shintaro Yamamichi, Senior Manager, Science Technology at IBM Research-Tokyo. Dr. Yamamichi cited three examples of how semiconductors uncover new technology frontiers. Computational materials discovery, a novel methodology, is the application of theory and computation to unearthing new materials and the key to enabling an ongoing stream of semiconductor innovation. In particular, using cognitive technology to mine huge volumes of literature reveal new insights into materials that uncover even more functionality such as greater conductivity and heat resistance. With new materials the oxygen of ever more advanced semiconductor chip manufacturing, the semiconductor industry will surely benefit from this methodology. The opportunity to accelerate quantum computing innovation is now. Launched in May 2016, the IBM Quantum Experience gives students, researchers and general science enthusiasts hands-on access to IBM’s experimental cloud-enabled quantum computing platform. The online platform features a forum for discussing quantum computing topics, tutorials on how to program IBM Q devices, and other educational material about quantum computing. Dr. Yamamichi encouraged the audience to join the program. The world’s tiniest computer, unveiled by IBM at the company’s Think 2018 conference in Las Vegas, packs several hundred thousand transistors and, IBM claims, the equivalent power of a 1990s x86 chip into a package smaller than a grain of salt. The computer’s small form factor (less than 1mm x 1mm) and low manufacturing cost means it can be embedded in product price tags and packages as an anti-fraud device using blockchain technology. Vehicles need to be both electric and intelligent as countries become more populous and traffic density increases. More drivers extend average drive time, boost greenhouse emissions, devour precious energy resources and lead to more traffic congestion and accidents. Dr. Haruyoshi Kumura, fellow at Nissan Motor, highlighted these issues in stressing the importance of a new era of intelligent mobility. To mitigate these problems, Nissan is focusing on the electrification and intelligence of its vehicles: Nissan’s electric vehicle, Leaf, reduces accidents with electric intelligence systems such as e-Pedal, which uses an accelerator pedal only for both acceleration and deceleration, and ProPILOT Park, a feature that automatically parks the car by using multiple cameras and ultrasonic sonars to detect pedestrians and other objects around the vehicle. With more than 90 percent of traffic accidents caused by driver error, Nissan plans to introduce autonomous driving on multi-lane highways by the end of 2018 and on city streets by 2020. By 2022, the company plans to roll out full autonomous driving to reduce traffic accidents caused by inattentive drivers. For full autonomous driving to materialize, sensor fusion technology must incorporate a combination of technologies – radar systems, light detection and ranging (LiDAR) systems and cameras – to identify the shapes and locations of nearby moving objects and measure their speed. Sensed information is then processed by a 3D graphic analyzer to make electric throttle, braking and steering decisions. The outlook for automotive industry includes car sharing and more electrification – both insights from Yoshiki Hayakashi, general manager, automotive solution strategic planning division at Toshiba Electronic Devices Storage, who offered his perspectives on trends in Japan’s automotive industry and beyond. To meet the requirements of the COP21 Paris agreement, the global automotive industry is shifting to electrification. Toshiba estimates 60 percent of new cars will be electric vehicles by 2040 to meet the International Energy Agency’s global EV outlook. In Japan, autonomous driving or advanced driver assistance systems (ADAS) will be offered in certain areas by 2020, the year of the Tokyo Olympic games. Growth of these advanced driving systems hinges on infrastructure development. Supporting data centers, intelligent transport systems, vehicle-to-everything connections, and smart city are all necessary components. Car ownership will begin to cede ground to car sharing with technology elites such as Tesla, Apple and Google leading the way. To expand the car-sharing industry, new alliances will take shape between new and old-guard automotive companies and electronics manufacturing services (EMS) providers. Autonomous driving requires precise 3D renderings of actual roadways using sensors for route mapping. While sensor fusion must be deployed for these capabilities, LiDAR offers better sensing range and space resolution precision than ultrasonic sonars, radars, and cameras. The next SEMI Japan members day is scheduled for October 30 in Tokyo. SEMI holds similar events in most regions where SEMI and its members operate. For the members events in your region, contact the SEMI office nearest you. Yoichiro Ando is a marketing director in SEMI Japan.

Storage and memory chipmaker and SEMI China member Tsinghua Unigroup is gearing up to meet burgeoning product demand with huge investments in its manufacturing plants. But the high-tech enterprise under Tsinghua University is eyeing a much bigger prize – growth of the region’s semiconductor industry and the realization of its ambition to become a more prominent force on the global stage.Inspired by the national strategy, the Tsinghua Unigroup’s big spends include USD 24 billion in Wuhan (Yangtze Memory Technologies Co., Ltd.,) USD 30 billion in Chengdu, USD 30 billion in Nanjing and USD 100 billion in Chongqing, said Liu Hongyu, senior vice president of Tsinghua Unigroup, speaking at the SEMI China Equipment and Materials Committee meeting last month.Advanced packaging is another rich vein of opportunity the region is tapping for expansion, said Liu Hongjun, vice president of China Wafer Level CSP Co., Ltd., another SEMI China member attending the event, hosted by NAURA in Beijing. Hongjun sees strong growth for Fan-in, Fan-out, FCBGA, 2.5D and 3DIC, with Fan-out out front. Liang Sheng, administrative commission director at BDA, a business advisory firm supporting high-technology manufacturing in the E-Town economic development zone, pointed to 5G chips and smart, networked electric automobiles as drivers of the next growth phase of Beijing’s integrated circuit (IC) industry.Global tailwinds are lifting China’s semiconductor industry and the region’s hopes, with SEMI and major industry analysts raising their semiconductor industry growth projects for 2018 to between 9 percent and 16 percent. According to SEMI’s latest market report, global semiconductor industry manufacturing equipment revenue reached USD 17 billion in the first quarter of 2018, logging all-time highs after jumping 12 percent from the previous quarter and 30 percent year-over-year. Korea was the top-performing region at USD 6.26 billion, followed by China at USD 2.64 billion.Tighter integration with the rest of the global semiconductor industry is critical to the growth of China’s chip sector, and SEMI China is squarely focused on this assimilation, said SEMI China president Lung Chu. The spearhead of this effort is the SEMI Innovation Investment Platform (SIIP) China, established by SEMI China last year to help grow China’s pool of skilled workers, promote advanced technology, generate industry capital, and expand China’s semiconductor industry while developing stronger connections with chip sectors in other regions. To strengthen ties with other regions, SIIP China will stage a number of innovation and investment forums this year including Chinese Night at SEMICON West (July 10-12) and a SIIP China Forum in Silicon Valley (July 15). In August, representatives from the Korea chip industry will visit counterparts in China (August), and a China delegation will travel to Japan for meetings (October). SIIP China is also strengthening the region’s links with Germany and Israel as SEMI serves as a crucial bridge between China’s semiconductor sector and the global industry.At the invitation of Shanghai authorities and the Ministry of Commerce of the People’s Republic of China, SEMI China in November will join the China International Export Import Exposition in Shanghai, an event that will underscore China’s commitment to the openness and cooperation of its semiconductor industry with the international chip community. As part of the exposition, SEMI will work with the Ministry of Commerce and domestic chip manufacturers to begin development of a special integrated circuit (IC) zone. SEMI China members are welcome to participate.With workforce development no less vital to the future of China’s semiconductor industry, the Equipment Materials Committee offered potential solutions to the industry’s talent gap. Measures included targeting university students and engineers with industry lectures and courses in key cities, campus recruiting, talent training that members said they are willing to help SEMI coordinate and stage and, much like the push to better integrate China with the global semiconductor industry, mobilizing member resources around a campaign to polish the image of the industry to make it more attractive to students and young workers. Members of the SEMI China Equipment Material Committee gathered at NAURA in Beijing in June for a warm and lively discussion about global semiconductor industry cooperation and growing China’s semiconductor sector.Cherry Sun is a marketing manager at SEMI China.

Standing-room only keynote speeches. A future awash in data amassed by transformative technologies and applications, with semiconductors at their core. Smart everything: Cars, medicine, manufacturing, workforce, you name it. The sheer numbers impressed as a record lineup of SEMICON West keynote speakers offered a glowing portrait of the future: The semiconductor industry stands on the cusp of a breakout expansion. Standing and seated shoulder-to-shoulder in the packed-to-gills opening keynote, the audience learned, indeed, that the best was yet to come: “This is the best SEMICON West, ever,” observed SEMI CEO Ajit Manocha. Here’s a glimpse of the keynotes by the numbers, starting with the luckiest of all. 7 – The number of keynotes – among the brightest lights in technology – sharing their visions of the future through the lens of breakthrough technologies that are nearly ready to make their indelible mark. Dozens of expert panelists also weighed in at SEMICON West, the annual U.S. flagship microelectronics gathering in San Francisco. 90 – The percentage of all data ever generated has been created in just the past two years as the cloud mushrooms with tweets, texts, emails, Facebook posts, YouTube videos, medical records and all manner of business information, noted Bill Bottoms, president and CEO of Third Millennium Test Solutions. In the years ahead, an almost unimaginable wealth of data will require analysis by artificial intelligence (AI) embedded in semiconductors to enable applications that go well beyond smart. 12-18 – That’s how many months it will take for data volume to double, predicted John Kelly III, IBM’s Senior VP, Cognitive Solutions. And it will double again and again, every 12-18 months. Kelly foresees a scale of growth “that will dwarf previous eras of computing … the number of opportunities is enormous.” Kelly’s four decades in computing gave considerable weight to his point that “in the industry, there has never been a more exciting point in time than today.” First – Technology is being re-born. Using baseball lingo, several speakers noted that we are just in “the first inning,” “the top half of the first inning” or “the beginning of the first inning” to make clear in the most emphatic terms the duration of prosperity that lies ahead for the industry. AI embedded in chips and demand for real-time analysis of AI data will be its fuel. As SEMI Americas president Dave Anderson observed with a smile, “We all know how long baseball games can go.” Third – That’s the current wave of machine learning the world is now experiencing, according to Sandia National Laboratories’ Principal Member Conrad James. Computers are now capable of solving many increasingly complex problems on their own, with no human intervention necessarily required, he said. 1000x – As spectacularly fast as computing power already is today, the industry will need to double that the rate of performance in the years ahead, predicted Applied Materials president and CEO Gary Dickerson. Demand for this herculean processing capacity will spur a “tremendous focus on innovation” among SEMI members, their customers and their customers’ customers. 5 to 15 – The remarkable amount of silicon that power today’s mobile devices will be overshadowed by the chips – equivalent in computing capacity to 5 to 15 cell phones – that will be the engine of self-driving and other features in future automobiles, predicted Pierre Ferragu, New Street Research Managing Partner, during the SEMI Bulls and Bears session. Automobiles with this souped-up computing capacity will sell in the millions worldwide in the years ahead, generating never-before-seen opportunities for the chip industry, he noted. 10,000 – It’s not just cars. Ten thousand is the number of sensors that will be built just into the wings of new Airbus A380-1000 aircraft, AMD CTO Mark Papermaster explained during his keynote. 10 terabits – The staggering amount of Facebook data uploaded daily in to the cloud, Papermaster noted. 1 Trillion – SEMI’s 2020 forecast that the industry will reach $500 billion in revenues by 2020 was eclipsed by one analyst, speaking at the SEMI Market Symposium on the first day of the event, predicted that the industry would top $1 trillion in the foreseeable future. SEMI’s Manocha later added that $1 trillion in industry revenue is possible by 2030, “maybe sooner.” 1 (sexy) coda – Coders are hip and software applications are the apple of the world’s eye. Even the most casual mobile device user knows that software apps makes it whirl. But “hardware is becoming sexy again,” said Applied Materials’ Dickerson, adding that equipment and other semiconductor hardware developed by SEMI members will enable the next great wave of global economic growth. Scott Stevens, SEMI

White House-led panel to address U.S. goal to lead in development of next-generation microelectronicsSEMICON West next week will host a White House-led discussion of the anticipated national leadership strategy for semiconductors, a multi-agency initiative led by top U.S. government national security and economic organizations.Next Wednesday, July 11, a panel of U.S. officials representing agencies involved in leading the strategy will address federal research and development (R D), investment and acquisition priorities aimed at ensuring the U.S. remains the global leader in the semiconductor industry.As global economic trends and technologies such as artificial intelligence evolve, and foreign governments increasingly lure microelectronics manufacturing investments overseas, the U.S. strategy for manufacturing advanced semiconductors and driving research and development (R D) in technology innovation has become an economic priority.The White House selected SEMICON West, organized by SEMI, as the site for the discussion and this urgent call to action because of the event’s central role in bringing together critical industries across the global electronics supply chain. The multi-agency panel will outline activities and new policies under development to ensure U.S. strategic leadership in microelectronics, including focused investment in innovations key to the next generation of devices for commercial and government use. The initiative also includes public-private partnerships to accelerate the capabilities of advanced semiconductors for critical applications such as artificial intelligence (AI), cyber, secure communications, the internet of things (IoT) and big data analytics.MEDIA WHO WISH TO ATTEND MUST CONTACT IN ADVANCE SCOTT STEVENS AT +1.512.288.4050 TO OBTAIN ACCESS BADGES PANEL: National Strategy for Semiconductor and Microelectronic Innovation TIME AND DATE: 10:30 to 11:30 a.m., Wednesday, July 11 LOCATION: Yerba Buena Theater, 700 Howard St., San Francisco MODERATOR: Dr. Lloyd Whitman, Principal Assistant Director, Physical Sciences and Engineering, White House Office of Science and Technology Policy PANELISTS: Dr. Sankar Basu, Program Director, Computer and Information Science and Engineering, National Science Foundation Dr. Eric W. Forsythe, Flexible Electronics Team Leader, U.S. Army Research Laboratory Dr. Jeremy Muldavin, Deputy Director of Defense Software Microelectronics Activities, Office of the Deputy Assistant Secretary of Defense for Systems Engineering Dr. Robinson Pino, Acting Research Division Director, Advanced Scientific Computing Research, Office of Science, Department of Energy SEMICON West is organized by SEMI Americas to connect more than 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing. SEMICON West is celebrating its 47th year as the flagship event for the semiconductor industry. Find more at www.semiconwest.org.MEDIA CONTACTS:Mike Hall, SEMI Global, +1.408.943.7988Scott Stevens, for SEMI Americas, +1.512.288.4050

Strong global semiconductor industry growth is helping power rapid expansion of China’s IC manufacturers in 2018, and continuing technology innovation is inspiring the region’s optimism over the long term, said Du Shanshan, senior analyst of SEMI China, at the recent SEMI China Member Day. The chief driving force behind this year’s growth of China’s IC industry is its equipment and materials market, with the sector riding a wave of a strengthening industrial infrastructure, a rapid increase of wafer manufacturing capacity, global leadership in new fab projects and large memory investments, Shanshan added. NAURA, a leading domestic provider of high-end IC equipment, is seeing robust growth after its push to recruit highly skilled talent and bolster its technology infrastructure, customer service system and supply chain, said Zhou Yang, vice president of Procurement at NAURA, which hosted the event. Yang said the key to NAURA’s success has been its unblinking focus on technology, product quality, fast product delivery, responsiveness to customer needs, cost controls, and environmental and social responsibility. Before visiting a NAURA factory, attendees reflected on how China’s IC manufacturers, using equipment and materials sourced domestically, seized the opportunity of global semiconductor growth to drive rapid local expansion. Excited about the growth potential of China's chip industry, members expressed their commitment to contributing to its independence and self-reliance. SEMI China Membership Grows Opening SEMI China Member Day, SEMI China president Lung Chu highlighted another expansion – SEMI China’s membership growth to nearly 400 companies, behind only the U.S. and Japan. Chu credited the increase, in part, to the steady growth of the global semiconductor industry. Chu said the increase also stems from the recognition that SEMI China is the China semiconductor industry’s best partner for fulfilling its ambition of becoming a more prominent player on the world stage. SEMI China’s member services platform that includes exhibitions and conferences, industry technical standards, industry research and analysis, a publicity apparatus and a talent development initiative provides powerful ways for the industry to Connect, Collaborate and Innovate. The platform enabled SEMICON China 2018 to set a booth and visitor record for the event, with attendees numbering 91,252, a highly successful 32 percent year-over-year growth. More than 50 SEMI member companies attended the 2018 SEMI China Member Day on June 6th in Beijing to explore opportunities for the global and Chinese semiconductor industry. Cherry Sun is a marketing manager at SEMI China.

The Advanced Lithography TechXPOT at this year’s SEMICON West will explore progress in extreme ultraviolet lithography (EUVL), its economic viability for high-volume manufacturing (HVM) and other lithography solutions that will address the march to 5nm and onward to 3nm.As a prelude to the event, SEMI asked Neeraj Khanna, Global Head of the Patterning Customer Engagement Team at KLA-Tencor, a speaker at the TechXPOT, for insights about the readiness of inspection and metrology tools for EUVL applications at 5nm and 3nm. For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.Neeraj Khanna, Global Head of the Patterning Customer Engagement Team at KLA-TencorSEMI: In general, how would you characterize the readiness of inspection and metrology tools intended for EUVL applications at 5nm and 3nm? In particular, what are some of the remaining research and development challenges that need to be addressed for each of these nodes?Neeraj Khanna: KLA-Tencor is working closely with its customers to qualify and ramp EUV. Our suite of inspection, metrology and data analytic solutions are being implemented to enable EUV infrastructure readiness including, for example, new reticle and resist qualification, scanner qualification, and EUV ramp preparation. These EUV integration activities require process control systems that support a wide range of applications, including hotspot discovery, lithography modeling, focus/dose process window qualification, reticle print check, mask blank inspection, and process and tool monitoring.As with any major technology inflection, it is critical to understand sources of process variation to enable ramp at optimal yield. For example, stochastics result in random pattern variations, which have a major impact on EUV yield. To manage stochastics, IC manufacturers are deploying process control solutions that support fast modeling of stochastic variations coupled with high-sensitivity, high-coverage wafer defect inspection. Another example is a methodology called hybrid scanner utilization whereby, when EUV scanners are implemented in production, they will only be used for a few layers, while all other layers will be patterned with 193i scanners. This technique requires tighter control and monitoring of overlay budgets.SEMI: How are you able to achieve this tighter control and monitoring?NK: To understand why hybrid scanner utilization requires tighter control and monitoring of overlay budgets, it’s important to outline how this differs from current scanner implementation. For critical layers in current process flows using 193i lithography, pattern layers for a given wafer are printed using the same stage/chuck on the same scanner. The overlay performance achieved using this lithography strategy is called dedicated chuck overlay (DCO). Use of a dedicated scanner and chuck for lithography reduces inter-scanner and inter-chuck distortion effects, resulting in DCO overlay error of less than 1nm. When EUVL is first implemented in production, it will be used for a few layers – likely, cut masks and contacts with eventual migration to metal 1 layers. All other layers will be patterned with 193i scanners. This hybrid scanner operation eliminates any possibility of using a dedicated scanner and dedicated chuck to support tight overlay performance specifications. Instead, fabs will be forced to optimize mix-and-match overlay (MMO), with the overlay performance obtained using different scanners for printing different layers on a given wafer.With overlay specifications for advanced DRAM and logic at ~2.5nm, fabs will need to implement strict 193i-to-EUV scanner matching strategies or risk consuming 60 to100 percent of the overlay budget on just MMO. To achieve tighter overlay control and monitoring required for MMO, fabs need to implement dense, in-field overlay error measurements that feed into scanner fleet management systems. KLA-Tencor’s ATL™ overlay metrology system supports a high measurement speed and the use of small in-die targets, enabling dense in-field overlay measurements with high accuracy. Our 5D Analyzer® data analytic and management system includes scanner fleet management capability that enables automatic product-based corrections to minimize MMO error, helping fabs reduce the risk to yield loss associated with a 193i-EUV mixed scanner implementation. SEMI: What other challenges do you see coming to the fore at 5nm and 3nm?NK: Overall, the 5nm and beyond design nodes will face challenges associated with new lithography technology, potential new device structures and smaller pattern pitches. IC manufacturers will require process control solutions that not only identify process windows, but also monitor patterning parameters and defectivity at multiple points to identify process shifts. To monitor dynamic processes at these advanced nodes, inspection and metrology tools will need to have both sensitivity to critical parameters/defects and robustness to process variation in order to provide IC engineers with smart feedback for efficient control of their processes.SEMI: Could you elaborate on what will be required to monitor patterning parameters and defectivity at multiple points? How different will the techniques be at 5nm/3nm vs. at say, 7nm or 10nm?NK: As an example of monitoring at multiple points, consider the transition to EUV lithography. With EUV, the cost per scan goes up dramatically. Thus, IC manufacturers will monitor parameters at multiple points to maximize yield and minimize risk: EUV reticle qualification requires inspection and metrology throughout the entire flow from mask blank manufacturing, to the mask shop, to the IC fab. For the advanced design nodes associated with EUV, wafer qualification requires monitoring and control of wafer defectivity, shape and geometry throughout the wafer manufacturing process. It also requires control of fab incoming wafer qualification while ensuring that fab-wide processes are meeting defect and shape standards necessary for printing smaller feature sizes. EUV resist characterization and qualification requires comprehensive lithography simulation, wafer defect inspection, and film thickness and uniformity measurements to help reduce development time and prepare the litho stacks for production ramp. As EUV scanners are ramping, fabs are faced with finding any unknown particle sources within the new scanner chambers. This situation is driving the need for tighter and more frequent PWP (particles per wafer pass) chamber monitors to ensure scanner cleanliness. In addition, EUV scanner qualification requires reticle front and backside particle checks, and hotspot discovery and process window qualification using optical wafer defect inspection and e-beam review. EUV process monitoring encompasses overlay error monitoring, focus/dose monitoring, critical dimension (CD) and 3D device shape monitoring, and continuous process window monitoring. EUV inline defect monitoring and tool monitoring is important for reducing baseline defectivity in the litho cell for faster ramp, and for early identification of litho excursions in production. A critical part of this monitoring strategy is inline after develop inspection (ADI) monitoring, which is defect inspection on patterned wafers after printing and development of the resist ADI. Inline ADI innovations that find yield-critical defects allow fabs to reduce process issues, prevent at-risk wafers early in the process, and enable rework when excursions are found in production. As with past technology transitions, the implementation of multiple monitoring steps as part of a comprehensive process control strategy will be critical for a fab’s successful ramp of EUV.Debra Vogler, SEMI