Technology and Trends

Presentations from SEMICON West’s “The Convergence of Semiconductor Manufacturing and Design” offer great insights into the collaboration between the two, as I was recently reminded by presenter Sutirtha Kabir, R D Engineering, Executive Director at Synopsys.Reviewing his talk “Revolutionizing Silicon to Systems Design: Unlocking the Future with 2.5D and 3D Multi-Die Innovations” was a good kick-off for our discussion that covered the continuous need for collaboration and where AI fits. Kabir, as I quickly learned, is a technical innovator and articulate communicator passionate about ongoing collaborations between design and manufacturing. Today’s blog post is the second in a four-part series featuring presentations from the SEMICON West design program, organized by the ESD Alliance, a SEMI Technology Community. The first blog, with Dave Kelf, CEO of Breker Verification Systems, appeared on January 6 (“Circular Collaboration Leverages EDA Advances”).Smith: How do you define collaboration between design and manufacturing?Kabir: Multi-die design and advanced packaging are a big focus of high-performance computing (HPC) and AI chips. Engineers are trailblazing and foundries are coming up with new stacking combinations. For this reason, design and manufacturing teams need to be closer than ever. Solutions must be made available to give ample visibility to manufacturing from the very start of the design process. Single die design has been done for 15 to 20 years with a continuity of power, area, and performance (PPA). Design flows, methodologies and the ecosystem between design houses, EDA vendors and foundries are mature and stable. The conundrum is that it's a different situation with multi-die designs. Not only is multi-die emerging rapidly, but the types of design innovations are different.We have been working closely with our foundry partners to move multi-die innovation forward by enabling more advanced process and packaging technologies. I don't see this slowing down as they are coming up with different ways of doing designs. Design teams are collaborating closely with the foundries to take advantage of the benefits of these new multi-die designs.Smith: You mentioned new stacking combinations and collaboration with the foundries. What about collaboration with the OSATs? Kabir: Generally, it’s both silicon foundries and OSATs. With advanced packaging, both play a significant role depending on the types of applications being targeted. Design house targets may shift from the traditional silicon foundry to several OSATs. For example, if an organic interposer is required, the collaboration could be with an OSAT in conjunction with the silicon foundry. There are many possible collaborations that may be required. The point I’m trying to make is that there is a strong need for collaboration between EDA and the foundries during design that continues through manufacturing and test.Smith: What trends in general are driving the need for this collaboration?Kabir: The trends are performance and scalability and the need for high-performance compute. Look at some of the mega-chip systems coming out today compared to the bigger systems from five years ago. HPC was not driving that much in 2.5D. The big interposers used to be on silicon, maybe 1.2 to somewhere around less than three reticle sizes. Today, the reticle limit is more than 5X. Leapfrog to today, and the configuration has changed where the state of the art is to use an organic interposer with multiple embedded bridges (up to 20 or more) buried inside the interposer to support high-speed interconnect. The organic interposer with multiple layers on the front side and back side communicates with bridges and the SoC and HBM that sit on top of that interposer.3D architectures stack dies with GPUs and a large amount of HBM such as an HBM4 memory stack. The memory stacks may be 8 or 16 high. All of this memory needs to be as close as possible to compute for scalability. In terms of the high-power demand, the designer needs to make sure that the voltage that is pushed from the bottom of the stack can feed the power hungry SoC blocks on top of the 3D stack. At the end of the day, EDA is all about giving design and manufacturing houses the capability to predict how a design is going to perform in all different kinds of scenarios. EDA must keep up with this trend and that requires collaboration.Smith: What about the verification side, specifically system verification? Kabir: Let’s say I am using a spreadsheet and doing back-of-the-napkin calculations, a technique that used to work well for single die or design blocks. Multi-die doesn't scale since multiple heterogeneous dies in a single package must be considered. Design planning must include directional changes to measure the effects with key performance indicators. The challenge is to correlate signoff and verification. Signoff engineers can no longer just verify at the end of the design cycle. Instead, it has become a continuous process that transcends the flow from design planning through implementation and signoff and release to manufacturing.The industry is repeating a pattern from about 20 years ago, when single-die design evolved from relatively naive approaches to much more sophisticated EDA-flow-driven methodologies.Smith: As you drive the tools forward, who are your counterparts on the manufacturing side? Kabir: It depends on the different stages of design—design planning, implementation or signoff. It starts at the architecture stage from the left when architects and physical design engineers are doing floorplanning. The term design technological co-optimization (DTCO) has evolved into S (system)TCO now because we are trying to co-optimize system design and technology. I'll give you a simple example. A working chip manufactured in a certain technology node is going to be used in a multi-die design. Is the existing chip technology good enough to support the design or will it require a new chip at a different node? In either case, how does an engineer work with the manufacturing house to make sure it has the right metal layers or a different number of metal layers or a different metal width or some other property on the technology side? Designers need to make data-driven decisions based on the configuration and technology numbers to meet power budgets.In the past, what was once managed through designer-ASIC house-manufacturing interactions are now increasingly being handled by EDA flows as part of design implementation.Smith: Ultimately, it's driven by business. The hard work and decisions are made by two teams of knowledgeable technical people who must come together.Kabir: And then of course it has to be rolled into program management, business development and all this needs to be supported by data. We all recognize that the design window is not increasing. It’s always about trying to get more out in less time with less people. That doesn't help the equation.Bob Smith: How does AI fit into this and how is it best leveraged? Kabir: I’m hearing, learning, and reading about the tremendous advantages AI could bring. AI has a huge role to play, but it won’t eliminate the need for savvy design and verification engineers.Multi-die design brings together different users from different tool backgrounds. Even the language between a packaging person and a silicon person is different. The terminologies they use are different, as are the ways they have done design over the last 15-20 years. The same applies to thermal, power or signal integrity engineering. Bringing them together requires that EDA will provide platforms where the whole system design, including chip design, is managed. That’s a tall ask for people from all different backgrounds to come in, learn different technologies and tools within a short time. This is where ChatGPT or Microsoft’s Co-Pilot can be applied in the EDA world today to quickly find solutions by reading through manuals, application notes, forums and the like to find solutions. This use of AI agents can save tremendous amounts of time for designers. Another aspect that can be positively impacted are roles. We have customers coming to us and brainstorming on the use of workflows and methodologies, instead of the design aspect. Scalability from the human perspective has become difficult because of the need to closely guide engineers to get them up to speed on new technologies and workflows. This is where Agentic AI can deliver a huge productivity boost. It's not replacing anyone. It's getting them to decisions and end results faster.Smith: Can Agentic AI play a big role? Kabir: Current AI is like the person who, when asked a question, has to give an answer even if it’s the wrong answer. The same thing is going to happen when we bring in all these EDA technologies with AI capabilities.The point I'm trying to make is how do we verify that AI is doing the right thing? In EDA, one of the biggest questions and concerns is if a result or outcome or design can be verified. If it can't be verified accurately, verification engineers will not trust what AI is telling them no matter how fantastic the algorithm is. The verifiability of AI solutions is important for EDA. The key question is: Why would I trust what your tool is telling me to do?EDA flows that are more mature rely on decades of expertise, thorough documentation, and various scenarios to train AI algorithms. Those are the AI-powered EDA flows that I trust the most. About Sutirtha KabirSutirtha Kabir, an Executive Director of R D for Synopsys’ 3DIC Compiler, has over 20 years of product engineering experience, driving, building, and inspiring teams across companies in the EDA industry. In his role at Synopsys, he supports construction and analysis of multi-die systems including stacked ICs plus Interposer configurations. Prior to joining Synopsys, Kabir was a Group Director of Engineering at Cadence. Kabir has a Master of Science degree in Electrical Engineering. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

2025 was a fast-paced, exciting, and impactful year for the SEMI Standards team. We developed 14 new standards on crucial topics like supply chain traceability, defect mitigation, compound semiconductor materials, and so many more. In addition, we introduced the SEMI Global Standards Summit (GSS) in North America, where we created new standardization roadmaps and continued pertinent sustainability conversations from the inaugural GSS at SEMICON Japan 2024. We’re also excited to announce that we closed out 2025 with an impactful Q4. From December 17-19, we held our SEMI International Standards Meetings during SEMICON Japan. More than 15 Task Force meetings and 5 Technical Committee meetings were held, followed by an award ceremony. The brand-new Digital Twins in Manufacturing Task Force was also established to define and standardize a digital twin framework that supports consistent and scalable implementations. We published the new SEMI T27 standard in Q4, and we celebrated several outstanding volunteers for their contributions to the SEMI Standards Program at both SEMICON West and SEMICON Europa. As we reflect on Q4, it’s apparent how important collaboration is to the success of SEMI Standards. By working together, we lay the foundation for groundbreaking innovations in microelectronics manufacturing. The SEMI Standards team would like to extend a warm and sincere thank you to everyone who donated their time and expertise to define the future of our industry. These efforts would not be possible without your commitment and support.Still, it’s never too late to join the SEMI Standards Program. Learn more about membership and how you can help influence the next phase of semiconductor manufacturing. Q4 2025 HighlightsTakeaways from the International Standards Meeting at SEMICON JapanIn Q4, the SEMI Standards team held its International Standards Meeting at SEMICON Japan, where several task forces convened to set standards for compound semiconductor materials, information and control, traceability, and more. From December 17-19 at Tokyo Big Sight, the SEMI Standards team supported these technical committees in advancing several key standards revisions, including SEMI E181, Specification for Panel FOUP for Panel Level Packaging, and SEMI E182, Specification for Panel FOUP Loadport for Panel Level Packaging. In addition, a new Maintenance Robot Communication (MRC) Task Force was established with the objective of defining communication protocols and data exchange specifications between maintenance robots and equipment.The next SEMI International Standards Meeting will take place from May 11-14 in Albany, New York, during the SEMI Advanced Semiconductor Manufacturing Conference (ASMC). Digital Twins in Manufacturing Task Force Although the terms “digital twins” and “digital twin frameworks” are becoming more prevalent in the semiconductor industry, there’s still much debate on what they cover. To develop concrete, standardized definitions for each, the SEMI Standards team established the Digital Twins in Manufacturing Task Force in Q4. After the task force defines these crucial terms, it will then create definitions for internal digital twin components outlining baseline capabilities, discovery mechanisms, prediction quality metrics, unified model interfaces, and lifecycle management. Eventually, the task force will outline a framework for Digital Twins compatible with existing guidelines like SEMI Standard E133 or ISO 23247. The SEMI Digital Twins in Manufacturing Task Force is open to industry stakeholders. To participate, join the SEMI International Standards Program or learn more. Standards Awards at SEMICON West and SEMICON Europa SEMICON West honoreesQ4 was also a time to celebrate some of the talented individuals who make a difference in the SEMI Standards Program. At SEMICON West and SEMICON Europa, we honored 25 accomplished industry leaders across the following five award categories for their commitment and participation. Merit Award winners led projects to successful completion at the task force level. SEMICON Europa honorees: Judith Wittmann, Cristina Sanna, Peter Wagner, Friedrich Passek, Frank Riedel SEMICON West honorees: Dave Dunne of Applied Materials, Kirsten Smith of UCT/ChemTrace, Tommaso Orzali of ASML, Dr. Tyler Harrison of Teledyne MEMS, and Dr. Mary Ann Maher of SoftMEMSSEMICON Europa honorees: Christian Kranert of Fraunhofer IISB, Enrica Cela of Soitec, Hans-Christian Alt of the Munich University of Applied Sciences, and Ulrich Kretzer of Freiberger Compound Materials GmbHLeadership Award winners bolstered the SEMI Standards program through member recruitment, mentoring, and training efforts. SEMICON West honorees: Michael Potts of Arcadis, David Kandiyeli of KINETICS Equipment Solutions Group, and Per Nelson of Daikin AmericaSEMICON Europa honorees: Frank Riedel and Judith Wittmann of Siltronic, Cristina Sanna of GlobalWafers, and Jochen Ruth of Pall CorporationHonor Award winners have demonstrated long-term dedication to advancing SEMI Standards.SEMICON West honorees: Steve Martell of Nordson Test Inspection Americas, Lucian Girlea of Nikon Precision, and Dave Huntley of PDF SolutionsSEMICON Europa honorees: Peter Wagner of SEMI Standards, Fritz Passek of Siltronic, Arnd Weber of SiCrystal GmbH, and Frank Petzold of trustsec IT solutions GmbHCorporate Device Member Award winners are participants from the user community who act as corporate representatives for the SEMI Standards Program from the device manufacturer side. Stefan Radloff of Intel was honored with this award at SEMICON West. Technical Editor Appreciation Award winners are adept at translating complex technical information into clear and precise language. Dr. Alissa M. Fitzgerald of A.M. Fitzgerald Associates became the award recipient in 2025. Workshops at SEMICON WestOn October 8, the SEMI Voltage Sag Immunity Task Force hosted its Enhancing Voltage Sag Immunity workshop to address fab downtime caused by voltage sags. The workshop convened more than 20 industry professionals to review the limitations of SEMI Standard F47. They found that while 20% of downtime instances can be attributed to three-phase events, SEMI Standard F47 does not require testing for such occurrences. As a result, the Voltage Sag Immunity Task Force is developing a draft revision of SEMI Standard F47, scheduled for balloting in March 2026. If you missed this workshop, you can access the recording and presentation here. October 8 also saw the exciting return of the Analytical Workshop, hosted by the SEMI Liquid Chemicals Committee after a multi-year hiatus. This year’s workshop addressed near-term challenges and advancements identified by the International Roadmap for Devices and Systems (IRDS). It covered chemical quality and consistency, trace metallic impurities and improvements in ICPMS instrumentation, automated instrumentation for online measurements, detection for particle precursors and sub-10nm particles in liquids and on-wafer, and organic particle precursors identification using FTIR-ATR, SERS and AFM-IR. If you missed this workshop, you can access the recording and presentation here. The 2026 call for abstracts will be announced soon. Lastly, the SEMI Standards and SEMI University teams worked together to host Semiconductor Device Manufacturing in a Cleanroom, a workshop meant to introduce best practices for overcoming contamination problems in the cleanroom. By reviewing different sources of contamination, reviewing analytical techniques for quality control, and performing cleanliness testing, the course aims to help cleanroom facilities improve production reliability and yield.New and Revised Standards Released in Q4October 2025November 2025December 2025Get InvolvedSEMI Standards development activities take place throughout the year in all major manufacturing regions. To participate, join the SEMI International Standards Program.SEMI Standards are available through individual download purchases or online via SEMIViews. Watch this video to learn more about how SEMIViews offers a cost-effective and streamlined way to access 1,110+ SEMI Standards. Sign up for a 30-day SEMIViews trial.For more information, please visit the Standards website and events page. For any questions regarding SEMI Standards activities, please contact your local SEMI Standards staff.Paul Trio is Director of Standards at SEMI.

Every time a transistor switches, it generates heat. Pack enough transistors together and you hit a wall: the chip melts before it computes. This thermal ceiling is why Splunk notes that "as physical and economic limitations are reached, the pace predicted by Moore's Law is slowing."Light solves this problem. Photons carry information without generating heat. Semiconductor Engineering details how heat dissipation and bandwidth bottlenecks make optical solutions the only viable path forward.But photonics introduces a different problem. Silicon has an indirect bandgap, which means it cannot emit light efficiently enough to produce lasers. Building photonic systems requires III-V compound semiconductors like indium phosphide (InP) and gallium arsenide (GaAs). These materials come with manufacturing constraints: InP substrates remain limited to 150mm, and GaAs wafers top out at 150mm, while silicon runs at standard industrial diameters of 200mm or 300mm. You cannot build a complete photonic system on silicon alone, so heterogeneous integration becomes mandatory. The result is that chief technology officers (CTOs) now manage two incompatible material systems, doubling technical complexity and supply chain risk.How Different Regions Are RespondingUnited States Intel has shipped 8 million photonic chips with 32 million integrated lasers. But the move that matters most is NVIDIA adopting TSMC-Broadcom co-packaged optics in its 2025 GB300 chips. When the dominant AI hardware company makes an architectural choice, competitors either follow or lose relevance.EuropeEuropean companies are solving their scale problem through consolidation. The market grew from €124.6 billion (2022) to a projected €175 billion (2027). Between January and June 2025, EPIC recorded 125 transactions worldwide, with European companies leading 50 of them. ZEISS established a new strategic business unit with €200 million in annual revenue across 6 countries. The strategy is to build on existing strengths in materials science and precision manufacturing.ChinaChina is building a parallel system designed for self-sufficiency. CHIPX produces 6-inch lithium niobate wafers with 110 GHz bandwidth, built despite U.S. export controls. This aligns with national policy: Xi Jinping chaired a February 2023 Politburo session focused on "basic research for self-reliance in science and technology." Optics Valley now hosts 5,000+ high-tech companies, targeting self-sufficiency within 4 years.Asia-PacificJapan, Taiwan, and India are combining strengths rather than building everything domestically. Japan committed $25.7 billion to semiconductor development between 2022 and 2025, and TSMC opened its first overseas R D facility there. India offers up to 50% capital support for photonics fabs and contributes 20% of global chip designers.The Next DecadeMarket projections vary wildly because the category spans everything from mature LED lightbulbs to emerging quantum computing systems. Mordor Intelligence projects growth from $1.75 trillion in 2025 to $2.39 trillion by 2030, while MarketsandMarkets forecasts $1.09 trillion to $1.48 trillion. This uncertainty matters because executives must commit billions in capital to technologies with decade-long development cycles.2025-2026The near-term focus is power efficiency. Traditional pluggable optical modules create 22 decibels of signal loss, requiring 30W per port to compensate. Co-packaged optics cuts power consumption by 3.5x. Ayar Labs' TeraPHY will deliver 8 Tb/s using UCIe standard packaging. In automotive, entry-level LiDAR drops to $200.2027-2032Quantum photonics moves from laboratory to commercial deployment. The market grows from $850 million in 2025 to $3.78 billion by 2030, with PsiQuantum partnering with GlobalFoundries to develop million-qubit systems by 2027. Unlike superconducting qubits requiring near-absolute-zero cooling, photonic qubits function at room temperature.2032-2035+The quantum market reaches $17.4 billion by 2035. Architectures combining analog, digital, quantum, photonic, and neuromorphic computing will require new transducer technologies, which means CTOs can no longer specialize in a single computing paradigm.Energy demand accelerates all of this. Data center electricity consumption will reach 945 TWh by 2030, and photonics can reduce that by over 50% by 2035.What This Means for LeadershipEach executive role faces a distinct version of the same problem: making decisions now about technologies that won't mature for years.Chief Executive OfficersCEOs face timing decisions with no clear answer. Adopt co-packaged optics in 2025-2026 and risk immature technology. Wait until 2028 and watch competitors capture market share. Japan's $25.7 billion commitment means smaller firms now compete against sovereign capital.Chief Technology OfficersCTOs must hold technical depth across incompatible domains. Silicon photonics, III-V materials, and thin-film lithium niobate each require different knowledge bases and supply chains. Most engineers specialize in one; photonics CTOs need working knowledge of all three while balancing 15-year development cycles against 2-year product roadmaps.Chief Financial OfficersCFOs must model returns on infrastructure that doesn't exist yet. The 50% power reduction from photonics changes total cost of ownership calculations, but boards need convincing before savings materialize.Corporate Boards Boards face a knowledge gap that affects governance quality. Most members don't understand why quantum-neuromorphic-photonic convergence matters at the business level. Leadership transitions signal consolidation is underway: IPG Photonics replaced its CEO in June 2024, Lumentum in February 2025.The Leadership ProblemFinding people who can run photonics companies is difficult because the field barely existed a decade ago. The technical knowledge lives in research labs. The business experience lives in traditional semiconductors. The people who combine both are rare.The broader market reflects this scarcity: over 330 R D vacancies appeared in the first half of 2025 alone. When technical roles are that hard to fill, executive searches require a global reach that most firms lack. In our searches, we regularly build single leadership teams by recruiting across China, Romania, Russia, the U.S., Germany, France, the UK, and India.The companies that figure out leadership first will have an advantage that compounds over years.About the AuthorsJan-Bart Smits is a Managing Partner at Stanton Chase Amsterdam. He serves as Global Subsector Leader for the Semiconductor industry and holds an M.Sc. in Astrophysics from Leiden University. David Harap is a Managing Director at Stanton Chase Austin with over 25 years of executive search experience. A Cornell University graduate and Father Kelly Scholar, he lectures at the University of Texas at Austin.

Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain.At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth trajectory of this critical sector and Europe’s potential to lead in next-generation packaging solutions.Market Momentum Fueled by AI and HPCRomain Fraux, Chief Research Officer at Yole Group, forecasted that global revenues for advanced packaging will grow from $46.1 billion in 2024 to $79.4 billion by 2030. “Everything is linked to AI and high-performance computing (HPC),” said Fraux, while also emphasizing the growing relevance of automotive applications in driving demand.Romain Fraux, Chief Research Officer, Yole GroupThis demand is accelerating innovation across the supply chain. One emerging area is panel-level packaging, which breaks away from traditional round wafers. As Andreas Wocko, Sales Manager at Lam Research, observed, “Since the 1970s, the semiconductor industry has built on wafers. Now we are not just scaling, we are reshaping, building in a square format for the first time” – an innovation which substantially increases area efficiency and reduces device cost. Andreas Wocko, Sales Manager Europe, Lam ResearchTechnology Transformation from Lab to FabEurope is already investing in the foundational technologies that will power tomorrow’s packaging systems. Rolf Aschenbrenner, Deputy Director of Fraunhofer IZM, the home of the European Union’s APECS advanced packaging pilot line, discussed ongoing research into functional interposers, routing density, and organic interposers. “Our goal is to show how a new design philosophy incorporating chiplets can be brought to the industrial systems level,” said Aschenbrenner.Rolf Aschenbrenner, Director Deputy, Fraunhofer IZMThese breakthroughs are essential, as pitch sizes shrink and new materials emerge. Dr. Jessica Stubbe, Global Application Manager at MKS Atotech, described how interconnect densities have doubled in the past two years, with the industry moving to pitch sizes of less than 10µm. Stubbe said this new technology “will be enabled by a move from traditional solder-based interconnects to copper-to-copper hybrid bonding to provide higher density I/Os and lower resistance.” Jessica Stubbe, Global Application Manager, MKS AtotechInnovation Meets Real-World IntegrationThis increased density carries thermal risks with it. As Ram Trichur, Global Head of Semiconductor Packaging at Henkel Corporation, said, “New architectures enabled by advanced packaging are putting power devices on the backside, interposer or substrate, and this addition of more power delivery components in the package creates more local hotspots.”The reduced feature sizes inside the latest packages make it more difficult than ever to apply thermal interface materials. “At Henkel, we are now making 1µm-level fillers which enable the effective filling of gaps as small as 7µm,” said Trichur.Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationOne of the applications which stands to gain the most from the development of advanced packaging technology is silicon photonics. Dr. Himani Kamineni, Director for Advanced Packaging at GlobalFoundries, described how co-packaged optics (CPO) brings photonics directly inside the package, reducing connection lengths from centimeters down to millimeters, and providing higher bandwidth and lower latency at lower power. “Advanced packaging and CPO are foundational elements for AI and data centers to enable scalability to the next generation of compute,” said Kamineni. “But it will need a lot of packaging innovation: silicon interposers, copper-to-copper interconnects, and fiber-attach units for precise alignment.” Himani Kamineni, Director, Advanced Packaging, GlobalFoundriesReliability and Test Under PressureIn the transition to new packaging technology, it is crucial that the industry does not lose sight of the reliability standards which have made semiconductors so valuable in sectors such as automotive and aerospace. Amar Mavinkurve, Director of Materials and Labs Package Innovation at NXP Semiconductors, warned the finer spacing and smaller feature sizes in the latest packages posed a problem for reliability and long-term performance. He said, “We are dealing now not just with one failure mechanism, but with multiple. So, the way that we are used to describing behavior in models will not necessarily hold in future. Even industry standards might not hold.”Discussing new technologies such as copper-to-copper interconnects, Mavinkurve pointed out that failure would not be due to a single event, but to processes such as electromigration, corrosion, and thermomechanical effects. To model reliability properly in future, he said, “we need to move from a physics of failure to a physics of degradation.” Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP SemiconductorsFabio Pizza, Business Segment Manager at Advantest Europe focused on quality and failure. With geometry scaling toward 1nm, early identification of known-good dies is essential to optimize cost and test coverage. Pizza said that, while device manufacturers need to keep time-to-market and the cost of test under tight control, they are also trying to figure out how to increase test coverage. “In a modern GPU, even a 100 DPPM quality process leaves 20 million transistors untested,” he said. Fabio Pizza, Business Segment Manager, Advantest EuropeEurope’s Position in the Global EcosystemThe conference concluded with a panel discussion about the prospects for Europe in the global advanced packaging market. According to Yole’s Romain Fraux, there is a strong ecosystem in Europe: “Europe’s strengths include specialized packaging service providers in the photonics and power market segments, as well as many packaging equipment manufacturers,” said Fraux. This resonated with the instincts of NXP’s Amar Mavinkurve and Advantest’s Fabio Pizza. Mavinkurve said: “We should focus on what we are already good at doing. It will be challenging to compete with advanced packaging providers elsewhere for AI and HPC business.”Ram Trichur of Henkel, however, urged the industry in Europe, “Do not take your foot off the gas on advanced packaging. You cannot do the full stack here, but in a technology such as CPO, there is a lot of innovation in Europe, and there is scope to add the manufacturing of these devices on top of the research capabilities.”Chris Scanlan, Senior Vice President of Technology at Besi, raised the idea of shifting production toward Eastern Europe. But Trichur cautioned that talent and infrastructure remain limiting factors in that strategy. From left to right: Chris Scanlan, Senior Vice President Technology, Besi;Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP Semiconductors; Fabio Pizza, Business Segment Manager, Advantest Europe; Rolf Aschenbrenner, Director Deputy, Fraunhofer IZM; Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationCollaboration is the Path ForwardSpeakers throughout the conference echoed a common message: advanced packaging is reshaping the semiconductor landscape, and global collaboration will be essential to success. “It is impossible for one country or one region to do the entire stack,” Trichur concluded. “Innovation must be matched with strategic partnerships to bring advanced packaging from research to real-world impact.”On behalf of SEMI, the SEMI Europe team would like to thank the industry leaders whose expertise and enthusiasm made this conference a resounding success. SEMI ContactCassandra Melvin, Senior Director of Business Development and OperationsEmail: [email protected]

In an era where performance and efficiency are essential, heterogeneous integration is rapidly becoming a foundational technology. The webinar “Heterogeneous Integration in Action: Powering the Next Era of Connectivity” featuring speakers from the HiCONNECTS project dives deep into the advances, challenges, and ecosystem-building necessary to bring next-generation integrated systems to life across Europe and beyond.HiCONNECTS (Heterogeneous Integration for Connectivity and Sustainability) brings together more than 60 partners across Europe under the Chips JU to explore how packaging, materials, architectures and software can be co-designed for industrial uptake.A Bold Ambition: Why This MattersConnectivity is the lifeblood of our digital age. From smart mobility and data centers to consumer electronics and factory automation, demands on performance, energy efficiency, miniaturization and flexibility keep growing.Heterogeneous integration offers a path to meet those demands by enabling dissimilar technologies, for example chips, sensors, RF, photonics, advanced packaging and AI accelerators to work together more seamlessly than ever before.Set against the backdrop of Europe’s broader ambitions under the EU Chips Act to strengthen its semiconductor ecosystem and technological leadership, projects like HiCONNECTS demonstrate how coordinated R D can translate into industrially relevant demonstrators and use cases.Key Themes from the WebinarBelow are some of the most compelling takeaways from the session:From Components to SystemsAcross all talks, one message was clear: heterogeneous integration is no longer just about better individual devices, it’s about system-level co-design.Speakers showed this in very concrete ways:In power device manufacturing, improving yield, process control and data correlation across the wafer line directly improves the reliability of integrated systems.In smart logistics and manufacturing, autonomous mobile robots combine LiDAR, cameras, 5G, on-board compute and collaborative AI to operate safely on factory floors.In life-science imaging, cryo-electron microscopes, AI-assisted screening and high-performance computing are tied together into a single workflow.In connected and autonomous mobility, radar, V2X modems, explainable AI software and human–machine interfaces form one integrated chain.You can no longer treat sensing, connectivity, compute and packaging in isolation – the value lies in how they are composed into complete systems.Ecosystem Consortium DynamicsTo realize heterogeneous integration, no single entity can go it alone. The webinar highlighted how large consortia such as HiCONNECTS bringing in universities, research institutes, packaging houses, system vendors, and tool suppliers are key. A strong theme: modularity and interfaces must be agreed upon early to allow parallel work across partners.Why Europe’s Timing is CriticalHiCONNECTS sits within a broader European push to strengthen the continent’s semiconductor capabilities and reduce systemic vulnerabilities in critical value chains. Europe already hosts strong players in photonics, packaging, system integration, robotics, automotive and research.What the webinar underscored is that coordination and shared infrastructure are now decisive:aligning manufacturing know-how with AI and data analytics,connecting application-driven demonstrators with underlying technology platforms, andensuring results can be replicated and scaled beyond a single lab or pilot line.Final ThoughtsThe “Heterogeneous Integration in Action” webinar was a timely, forward-looking snapshot of how Europe’s microelectronics ecosystem is moving from component-level innovation to system-level co-design, grounded in real industrial use cases.The journey is far from complete, but the payoff is clear: higher-performance systems, new classes of products in mobility, health and manufacturing, and a stronger, more resilient European position in semiconductors.Kartikey Srivastava, Manager, EU ProjectsSEMI Europe Phone: +49 151 1436 6324Email: [email protected]

The SEMICON West 2025 design program “The Convergence of Semiconductor Manufacturing and Design,” organized by the ESD Alliance (ESDA), a SEMI Technology Community, featured presentations about successful collaborations between the design and manufacturing markets. The three-hour program in a packed conference room included plenty of great material that we’re using as the basis for a blog series that you will see over the next several months. I’m working on them now based on my conversations with four of the speakers where we discuss key drivers behind the need for collaboration and what’s ahead.I’m starting with Dave Kelf, CEO of Breker Verification Systems, a company steeped in front-end chip verification, who describes an actual circular collaboration that effectively leverages AI and other electronic design automation (EDA) advances. We recently talked about collaboration, integrated design and manufacturing flows and AI.Smith: How does Breker define collaboration between design and manufacturing? Kelf: In general, at a technical level, we would define this collaboration as the sharing of data, methodology and/or information that improves both processes. As semiconductors become more complex, this sharing process is increasingly important to effectively manage the overall complexity of today’s chip designs.Smith: What trends are driving the need for this collaboration?Kelf: Apart from the ever-increasing size and density of semiconductors, there are specific trends that require more interaction between design, verification and manufacturing. Obvious developments include the advent of chiplets, given the changes in performance of signal paths, and 3D devices driving complex packaging, power dissipation and other issues. Design issues such as the increased need for SoC coherency testing and complex device structures such as multi-core processors, also play a role. With many of these issues, design and verification (D/V) trade-offs have an impact on manufacturing, and vice versa. For example, differing delays on a Universal Chiplet Interconnect Express (UCIe) interface—an open specification for a die-to-die interconnect and serial bus between chiplets—will have an impact on hazard testing in coherency verification. As another example, thermal hotspots on some parts of a chip package might need additional testing during the verification phase. Smith: What trends and challenges are preventing a fully integrated design and manufacturing design flow?Kelf: Traditionally, the D/V and manufacturing teams have remained separate in most organizations, as well as between the two industries. EDA companies sell primarily to the design teams, although they do interact with the foundries at the back end of the process. Manufacturing companies work directly with different teams at the foundries and not with the D/V teams at all. New relationships need to be built up. The general know-how in these disciplines is different, and methodology approaches tend to be disconnected. The tradition is to separate the processes and use standardized interfaces for communication that leaves little room for improvisation. All this needs to change so that teams can begin to work more closely.Smith: What is circular EDA-manufacturing collaboration and vertical integration?Kelf: In past EDA flows, we have seen disparate tools performing specific functions. As semiconductors got smaller, their physics changed and this led to the design process absorbing new characteristics. For example, abstract designs were run through synthesis to create gates connected by wires. This format was then passed to place and route (P R) tools that would lay out the gates in terms of transistors and interconnects on the silicon wafer. On large devices, the gate level signal delays were larger than the interconnect, allowing design to be separated from layout. As silicon became denser, the interconnect delays became the dominant factor, and the layout of the device impacted the design synthesis process. The two tools required forward integration—synthesis projected layout rules to P R, and a reverse integration where layout characteristics were sent back to synthesis for redesign where required delays could not be handled during P R. The methodology went from a simple flow to a circular design approach as synthesis and P R cooperated. The same is now true of design and manufacturing where solving the problems noted above requires this same circular cooperation. Smith: What will it take to have an integrated design and manufacturing flow?Kelf: A lot of cooperation between different groups. As we reach limits in areas such as signal integrity and thermal management that will squeeze silicon efficiency improvements, these methodology linkages will be required for continued progress and growth. The industry (both design and manufacturing) will be highly motivated to make this happen. Smith: From a personnel perspective, who (on both sides) are the typical touchpoints? Kelf: It will be the engineering staff from both the design side and manufacturing that work closely to develop technical solutions. Executive-level support is, of course, needed to cement the collaboration. Smith: Where does AI fit?Kelf: AI will have a role to play in this. Estimating the factors that drive efficient design to manufacturing to design flows is a critical step in speeding interaction and providing sensible estimated starting points. AI can process the large amounts of data necessary to provide these estimates as we now see complex chips that contain billions of transistors. AI will be needed to accelerate the interactions for different tools through the development process.As design and manufacturing collaboration becomes a critically important industry strategy, companies are turning to SEMI and its Technical Communities such as the ESDA and their wide-ranging initiatives. For details and to get involved, visit the ESDA website at https://semi.huihuidehui.workers.dev/en/communities/esda. To learn more about Breker and its solutions that provide test content portability and reuse to solve complex semiconductor challenges across the functional verification process, go to: https://brekersystems.com.About Dave KelfDave Kelf holds the position of CEO of Breker Verification after serving as its Chief Marketing Officer responsible for all aspects of Breker’s marketing activities, strategic programs and channel management.Earlier, he served as vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions, was president and CEO of Sigmatix, Inc., and held senior positions at Cadence, Synopsys and Springsoft. Kelf holds a Bachelor of Science degree in Electronic Computer Systems from the University of Salford and a Master of Science degree in Microelectronics from Brunel University, both in the U.K., and an MBA from Boston University.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

Silicon carbide (SiC) has become a cornerstone of next-generation power electronics, driving advancements in electric vehicles, renewable energy, and industrial applications. After several years of rapid capacity expansion, the SiC industry is now entering a new phase focused on optimization, quality, and long-term scalability.This transition reflects a broader realignment across the global semiconductor ecosystem. As new fabs come online and supply chains mature, the industry is prioritizing stability, cost efficiency, and technical excellence over sheer capacity growth. SiC has moved from being a niche technology to a critical enabler of the energy transition, and this maturity demands not only investment in tools and materials, but also in process knowledge, cross-industry standards, and long-term partnerships that can sustain innovation at scale.To understand how this shift is unfolding, SEMI Europe spoke with Dr. Mark Puttock, Senior Director, Technology and Innovation at Entegris. Puttock shared his perspective on the industry’s evolution and how strategic collaboration and process innovation are shaping the next chapter of SiC manufacturing.From Ramp-Up to RefinementThe early growth of SiC manufacturing was driven by surging demand for high-efficiency power devices, particularly in electric vehicles. According to Puttock, that expansion period has given way to a new focus on yield, uniformity, and process control.The industry is entering a stage of maturity where success depends on optimization rather than scale alone. Improving consistency across crystal growth, wafer, and device fabrication is becoming just as important as adding capacity. This refinement phase calls for closer integration between materials science and manufacturing technology to ensure reliability and cost efficiency.A Focus on Process and Materials InnovationAs SiC moves toward high-volume production, challenges related to contamination control, defectivity, and wafer uniformity are taking center stage. Puttock noted that addressing these issues requires collaboration between materials suppliers, equipment manufacturers, and device makers.Efforts across the industry are converging on similar goals: enhancing purity, improving process repeatability, and developing new methods to enable larger wafer formats. Moving from 6-inch to 8-inch SiC wafers, for example, is widely recognized as a key step toward higher throughput and cost efficiency. Puttock emphasized that innovation in materials science and manufacturing technology must go hand in hand to support this scaling trend.Insights from Cross-Industry CollaborationA recent Entegris blog post featuring insights from Volkswagen Group Components and Porsche Consulting explores how SiC adoption is reshaping manufacturing strategies beyond the semiconductor industry. The post also highlights the strategy paper developed by Porsche Consulting in collaboration with Entegris. This joint effort demonstrates the value of aligning semiconductor-grade precision with automotive manufacturing demands. By sharing perspectives across industries, partners can accelerate best-practice adoption and strengthen the overall ecosystem for wide-bandgap technologies.Building a Sustainable FutureSustainability remains an integral part of this optimization phase. SiC devices themselves enable energy efficiency in end applications, but the way they are manufactured is equally important. Optimizing material use, recycling process consumables, and improving chemical delivery efficiency all contribute to a smaller environmental footprint. As production scales, attention to both performance and sustainability will be key to long-term success.Looking ForwardThe transition from expansion to optimization marks a pivotal moment for SiC manufacturing. Industry focus is shifting from building capacity to mastering control, quality, and resource efficiency. Puttock sees the future of SiC as one shaped by deeper digital integration, data-driven process development, and continued collaboration across disciplines. These advancements will help enable more consistent, sustainable, and cost-effective production—laying the foundation for the next generation of high-performance power devices.At the same time, Entegris continues to invest in materials science, contamination control, and advanced process technologies that help its customers overcome the complex challenges of SiC manufacturing. By combining technical expertise with a collaborative approach, the company plays an active role in supporting the industry’s transition toward more efficient and sustainable production.James Lam is Business Development Manager at SEMI Europe.

The semiconductor industry is undergoing a rapid transformation. Artificial intelligence (AI) applications, such as agentic and physical AI, push compute demands to unprecedented heights, prompting the semiconductor industry to push the boundaries of 2nm technology and beyond. Yet, as we move to these advanced semiconductor technology nodes, it has become increasingly challenging for academic research to remain closely connected with the fast-evolving industrial developments, limiting academic researchers in driving innovation. Europe’s NanoIC pilot line, a pioneering European initiative, hosted by imec, is addressing this challenge by offering pathfinding process design kits (P-PDKs). To cover the potential of these P-PDKs and their impact on Europe’s semiconductor ecosystem, we sat together with Professor Mehdi Tahoori (professor at Karlsruhe Institute of Technology) and Anita Farokhnejad (DTCO Program Manager at imec).SEMI: What exactly is a P-PDK, and how does it differ from traditional PDKs?Farokhnejad: At its core, a process design kit (PDK) is a software environment that enables circuit designers to simulate, validate, and optimize chip designs using realistic models of chip technology. Consider it a blueprint or a simulation toolkit allowing chip designers to explore performance, power, and manufacturability of a new chip architecture in a virtual sandbox. What sets P-PDKs apart is that they anticipate future technologies. Unlike traditional PDKs, which are based on existing technologies, P-PDKs are built on predictive models of future nodes and architectures. This allows researchers to explore system-level trade-offs, assess architectural implications, and prepare design flows before a technology reaches maturity. SEMI: Why are they so crucial for academia?Tahoori: For decades, academic researchers could contribute to semiconductor innovation using abstraction layers that allowed them to design and test new architectures without direct access to the latest technologies. This approach worked well until the industry reached the 20-nanometer node. At that point, the complexity of semiconductor design increased, with the introduction of advanced device architectures like FinFETs, nanosheets, Forksheets, CFETs, and novel integration solutions such as 3D stacking and chiplet integration.Transistor scaling in the AI eraTraditional abstraction models could no longer keep up with these advances, and the gap between academic research and industrial practice began to widen. This growing gap started to limit academia’s ability to participate in semiconductor paradigm shifts, such as CMOS 2.0 and new computing architectures. P-PDKs, enabled by the NanoIC pilot line, aim to bridge this gap, restoring the connection between academic thinking and industrial progress.SEMI: How does this support semiconductor innovation in Europe?Tahoori: Universities are ideally positioned to drive out-of-the-box innovation and invent new paradigms for computing. This is where universities truly excel. But to do that, they need access to the latest technologies and tools. We see for example a strong focus on the AI revolution and how the microelectronics industry is enabling that transformation. To meet the demands of AI applications and the computing power they require, we need to design new computing architectures based on advanced technology nodes. This is precisely the academic area of expertise. To design these new AI computing architectures, however, we need the most advanced technologies available. The P-PDKs for advanced nodes provided by the NanoIC pilot line now make this kind of research possible at universities. Something that was not feasible before.Additionally, the P-PDKs also provide an important reference technology and platform to benchmark and validate these innovations within a next-generation design roadmap. This means researchers can test their novel architectures against realistic process and performance metrics.SEMI: Are they only available for academia?Farokhnejad: The NanoIC P-PDKs are meant to be accessible to foster innovation across Europe’s semiconductor ecosystem. These advanced PDKs are therefore also available to European research organizations, startups, and industry partners. Access is facilitated through Europractice, where eligible users can apply by signing a Design Kit License Agreement (DKLA). Once approved, they gain access to the PDKs.SEMI: What other technology nodes are NanoIC’s PDKs addressing?Farokhnejad: The first P-PDK was released in June (first version of the N2) and supports frontside and backside routing with TSVM, standard cell libraries, and multiple VT flavors for early-stage design exploration. Upcoming releases include new versions of the N2 P-PDK, as well as A14 and A7 PDKs, eDRAM and SOT memory PDKs, and advanced interconnect solutions such as redistribution layers (RDL), hybrid bonding, and interposers.Those interested in learning more about the NanoIC ecosystem and the research enabled by the P-PDKs can meet representatives and partners of the NanoIC pilot line during SEMICON Europa, November 18-21 at booth C2417 in Messe Munchen. More information about the initiative is also available on the NanoIC website.BiosMehdi Tahoori, Professor Chair of Dependable Nano-Computing - Karlsruhe Institute of Technology Mehdi B. Tahoori is Professor and Chair of Dependable Nano-Computing at the Karlsruhe Institute of Technology (KIT), Germany, and guest professor at imec, focusing on CMOS 2.0 and future chip technologies. He previously worked at Xilinx (USA), Fujitsu Labs (USA), and served as a junior professor at Boston Northeastern University (USA) and as a visiting professor at the University of Tokyo (Japan). He earned his B.S. from Sharif University (Iran) and M.S./Ph.D. from Stanford (USA). Prof. Tahoori is Deputy Editor-in-Chief of IEEE Design and Test Magazine, is a former Editor-in-Chief of Elsevier Microelectronic Reliability and has chaired major IEEE symposia. His honors include multiple best paper nominations and conference awards, the US National Science Foundation Early Faculty Development (CAREER) Award (2008), an ERC Advanced Grant (2022), and an IEEE fellowship.Anita Farokhnejad, DTCO Program Manager - imec Anita Farokhnejad earned her PhD from Universitat Rovira i Virgili (Spain), specializing in FEOL and device modelling. She joined imec in 2021 as an R D Engineer, focusing on BEOL optimization and future roadmap development. Collaborating closely with integration and physical design teams, she develops models for PnR data analysis and BEOL optimization. Her recent work on the enhanced Ring Oscillator (eRO) model aids in the early assessment of new materials and BEOL boosters. In August 2023, she advanced to team lead for PDK Enablement, translating advanced semiconductor nodes into Pathfinding-PDKs. Farokhnejad is also dedicated to education, conducting courses that make sophisticated technological concepts accessible to both industry veterans and aspiring engineers. Currently, she serves as Program Manager of DTCO at imec, where her contributions continue to drive innovation in the semiconductor industry.AcknowledgementThis work was enabled by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union’s Digital Europe (101183266) and Horizon Europe programs (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland and Romania. For more information, visit https://www.nanoic-project.eu.DisclaimerFunded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or Chips Joint Undertaking. Neither the European Union nor the granting authority can be held responsible for them. SEMI ContactJames Lam, Business Development ManagerEmail: [email protected]

Q3 2025 was packed with activity. From finalizing the Standards program for SEMICON West, to organizing the event’s corresponding Global Standards Summit (GSS), the Standards team is excited to share its most recent quarterly developments.On Tuesday, October 7, leaders from across the industry convened in Phoenix, Arizona, for the second annual GSS. This half-day summit focused on future standardization needs for supply chain traceability and environmental sustainability. In addition, the Standards team conducted two workshops at SEMICON West. The first, SEMI Liquid Chemicals Analytical Workshop, detailed recent advances in analytical methodology and instrumentation related to particle measurement, trace metals, and organics in liquid chemicals. The second, Enhancing Voltage Sag Immunity: SEMI F47 Standards Updates Insights Workshop, offered a forum for sharing improvements to SEMI Standard F47 to further enhance tool performance and reliability. Finally, Q3 saw the official introduction of SEMI Standards T26 and E195. SEMI T26-0925, Specification for Electronic Supply Chain Traceability Using Distributed Ledger Technology, will be crucial for improving security and transparency for the industry’s supply chain. Additionally, SEMI E195-0925 is now available for purchase. This standard, Test Method Using Adhesive Replacement Substrates to Assess Particulate Surface Contamination on Critical Chamber Components, offers a testing approach for measuring the ISO 14644-9 cleanliness of a critical chamber component.To participate in upcoming standard developments, learn more about becoming a member of the SEMI International Standards Program. Global Standards Summit The SEMI GSS made its North American debut at this year’s SEMICON West in Phoenix. Building on its inaugural event at SEMICON Japan 2024, GSS is a strategic forum dedicated to creating an industry-wide standardization roadmap for the next three and seven-year benchmarks. The 2025 GSS continued conversations from SEMICON Japan on environmental sustainability, while expanding its program to include supply chain traceability. As geopolitical tensions, mounting cybersecurity threats, and rising technological demands continue testing the limits of the industry’s supply chain, the need for global standardization is becoming increasingly apparent. The 2025 GSS program addressed these concerns and others across multiple sessions, offering insight on how these challenges are being addressed in the industry while highlighting critical areas still in need for standards development. Key outcomes from the GSS program include: Addressing data sharing across multiple supply chain tiers while protecting IP rights and a call for harmonization across standards. The presentation by Randy Hall from the Provenance Chain Network, offered approaches on how data owners can share information with authorized users without compromising sensitive manufacturing details. While there are standards gaps that hinder broader adoption, there is opportunity to address insufficient visibility across the industry’s supply chain amid ongoing cybersecurity threats by harmonizing across existing standards implementations. An integrated modeling framework for informing energy efficiency and carbon reduction approaches. Developed by the International Roadmap for Devices and Systems (IRDS) Environmental Sustainability for Semiconductor Facilities (ESSF) team, this effort helps address demands for maintaining rapid technological progress while still meeting the industry’s ambitious sustainability goals.Standardization opportunities for improving sustainability within manufacturing facilities. Nate Monosoff from Jacobs offered insight into the decision-making tradeoffs that balance sustainability with other facility performance areas, focusing on standard methods for calculating ESG performance. GSS concluded with a panel discussion that featured leaders from AMD, FTD Solutions, Intel, The Provenance Chain Network, Jacobs, Qualcomm, and Tokyo Electron. In this session, our thought leaders discussed the fundamental importance of standardization for our industry, standards adoption, incentivizing stakeholders, and how standards can be designed to remain flexible and adaptive as technologies and regulatory landscapes evolve. SEMI Standard T26In line with the 2025 GSS theme of supply chain traceability, the Standards team is pleased to introduce SEMI T26, Specification for Electronic Supply Chain Traceability Using Distributed Ledger Technology. This standard was published in September to define a secure and decentralized traceability system that all members of the electronics supply chain can safely share. This system is based on distributed ledger technology to improve industry-wide reliability assurance.Update on Document 7130CIn February, Document 7130C was approved during the North America Metrics Technical Committee Chapter Meeting. The document officially became SEMI E195 - Test Method Using Adhesive Replacement Substrates to Assess Particulate Surface Contamination of Critical Chamber Components in September.SEMI E195 describes a quantitative method for measuring the ISO 14644-9 surface cleanliness for particle concentration of a critical chamber component (CCC), by means of an adhesive replacement substrate. The purpose of this standard is to ensure measuring and reporting consistency across CCCs or processing equipment manufacturers. To help acquaint the industry with this standard, SEMI offered a combined, in-person course on SEMI E194 and SEMI E195 during SEMICON West. The course provided fundamental information on each standard, in addition to other process approaches for improving reliability and yield.Other SEMI Updates:SEMI Preventive Maintenance Automation White Paper SEMI Korea conducted a Global PM Automation Survey in August to better understand today’s preventive maintenance readiness issues for autonomous fabs. The results will be included in SEMI’s upcoming PM Automation Whitepaper and will ultimately guide future developments for related SEMI Standards. Standardized Semiconductor Cyber Assessment FrameworkIn Q3, the Semiconductor Manufacturing Cybersecurity Consortium (SMCC) released its Standardized Semiconductor Cyber Assessment (SSCA) framework. This document provides a detailed cybersecurity readiness plan for semiconductor companies across the supply chain. Its goals are to standardize industry-wide cybersecurity risk evaluations, establish and accelerate the adoption of best practices, and improve information sharing and collaboration. Download the SSCA framework for free.New Data Standard for Equipment Edge Governance In June, Document 6938C was approved during the Taiwan Information Control Technical Committee Chapter Meeting. The document officially became SEMI E196 - Guide for Equipment Edge Data Governance. SEMI E196 provides guidance for identifying equipment data supplied by manufacturers that can be used in equipment engineering or analysis applications.New Guide to Meet IRDS Yield Table RecommendationsAt the NA Summer Meetings, Document 6601B passed TC Chapter review with technical changes and a Ratification Ballot was issued in Cycle 7-2025. Pending final Procedural Review, Guide for Meeting IRDS Yield Table Recommendations for High Purity Polymer Materials and Components Used in Ultrapure Water, will cover areas that establish criteria for allowable contribution by critical components used for UPW treatment plant and distribution system. This document will be proactively updated to manage the risks associated with the high purity polymer materials used in the semiconductor process. The biggest challenges today are metals and particles and certain organics.Flex Standards Meeting at FLEX 2026Meet the leaders of the SEMI Standards Flexible Hybrid Electronics (FHE) Task Forces at Flex 2026, in Arizona, February 24-26, and learn about ongoing FHE standardization efforts!Standards Introduced in Q3 2025New and revised standards released in Q3. July 2025 StandardsAugust 2025 StandardsSeptember 2025 Standards Get InvolvedSEMI Standards development activities take place throughout the year in all major manufacturing regions. To participate, join the SEMI International Standards Program.SEMI Standards are available through individual download purchases or online via SEMIViews. Sign up for a 30-day SEMIViews trial.For more information, please visit the Standards website and events page. For any questions regarding SEMI Standards activities, please contact your local SEMI Standards staff. Paul Trio is Director of Standards at SEMI.

Atomic layer deposition (ALD) and atomic layer etching (ALE) are transforming the way semiconductors are built—layer by layer, atom by atom. These atomic-scale processes are essential to scaling future transistors, improving memory, and enabling next-generation device architectures.SEMI spoke with Sergei Ivanov, Business Technology Director of Metallics R D and Balaji Kannan, Business Technology Director of Dielectrics R D and from Merck KGaA, Darmstadt, Germany to learn about their latest material innovations. At the company’s Electronics business, materials scientists and process engineers are advancing atomic-scale engineering to address some of the semiconductor industry’s toughest challenges. From novel deposition chemistries to next-generation etch techniques, their work is helping to enable future logic, memory, and specialty devices.Pushing the Boundaries of ALD Precursor ChemistryAtomic Layer Deposition (ALD) remains a cornerstone technology for scaling transistors and enabling new architectures. Materials scientists at Merck KGaA, Darmstadt, Germany are exploring novel precursors that enhance film quality, streamline processes, and expand the operational window for complex structures:One area of focus is next-generation hafnium and zirconium precursors. “These advanced high-k dielectrics offer better thermal stability, improved step coverage, and reduced impurities while achieving higher k-values,” Sergei Ivanov explained. “Such attributes are essential for logic and memory devices that demand reliable dielectric performance with minimal defect density.”Another important development is area selective deposition (ASD). Merck KGaA, Darmstadt, Germany’s small-molecule inhibitor solutions reduce the need for advanced patterning in narrow dimensions and 3D geometries, enabling cost-effective and simpler integration for leading-edge nodes. Their selective co-reactants platform leverages digitalization techniques including multivariate analysis, digital twin technology, and machine learning to accelerate process development for critical ASD applications. This approach facilitated industry-first adoption of ASD in high volume manufacturing and enables an ever-expanding toolbox of OEM processes for ASD of high-k, Ti, Mo, Si and other thin films.Merck KGaA, Darmstadt, Germany is also broadening the scope of ALD chemistries across the periodic table. “As our customers encounter new technical challenges, we continue to expand our R D scope across new elements and ligands. Examples include europium, lanthanum, scandium, and cerium dopants with improved electrical properties, niobium and vanadium precursors for deposition of nitride and oxide films with reduced impurities and improved ALD performance, and high-performance nickel MILC solutions are finding their way out of our labs and into customer roadmaps at an ever-accelerating pace,” said Sergei Ivanov.The company’s role in molybdenum chemistry is another example. Merck KGaA, Darmstadt, Germany is a key producer of molybdenum precursors including MoO2Cl2 with industry-leading quality, density, and container utilization. The company offers MoCl5 with advanced trace impurity control paired with innovative container technology. The company’s next-generation organic metallic molybdenum precursors incorporate novel ligands that contribute to critical gains in device performance.Merck KGaA, Darmstadt, Germany’s work with organosilane precursors is also opening new possibilities. “For gate-all-around (GAA) transistor technology, precursors incorporating novel bonding structures enable highly conformal dielectric films with excellent electrical and physical properties, even in complex 3D geometries. At the same time, organosilane chemistries designed to increase silicon incorporation during deposition are supporting high-growth-rate oxides for gapfill applications, delivering the thick films required with greater throughput,” said Balaji Kannan. “Together, these innovations highlight how tailored precursor design can address both scaling challenges and manufacturability in next-generation devices.” Driving Selective and Sustainable Atomic Layer Etching (ALE)“Precision in etching is as critical as deposition. Our innovations in ALE are designed to provide ultra-selective, low-damage material removal, which is increasingly vital as device geometries become finer and more complex,” Sergei Ivanov shared. One example is metal-free ligand exchange ALE for high-k materials, where Merck KGaA, Darmstadt, Germany’s research into etching HfO₂, ZrO₂, and HfZrO₄ showcases a novel metal-free approach. This technique enables accurate and damage-minimized etching of high-k dielectrics, which is essential for integrating advanced transistors and memory stacks.These advancements address industry-wide concerns regarding pattern fidelity, material selectivity, and plasma-induced damage, ensuring greater process control and extending the lifetimes of devices.Looking AheadMerck KGaA, Darmstadt, Germany’s strategic commitment to semiconductor innovation includes ongoing R D efforts that reflect the vision of its Electronics business: providing material-centric solutions to the industry’s most complex integration and performance challenges. Whether advancing front-end device scaling or developing breakthrough materials for emerging applications, the Electronics business of Merck KGaA, Darmstadt, Germany is committed to shaping the materials roadmap for a more connected, intelligent, and efficient world.James Lam is Business Development Manager at SEMI Europe.