Technology and Trends

With increasing demand for personalized smart devices, the MEMS and sensor market is undergoing rapid transformation. MEMS sensors are the backbone of smart wearable devices, seamlessly integrating multiple functions to monitor and simplify our day-to-day activities. As applications in healthcare, environmental tracking, and AR/VR expand, the need for ultra-compact, energy-efficient, and intelligent sensors is more critical than ever.In an exclusive conversation with SEMI, Stefan Finkbeiner, CEO of Bosch Sensortec, shared his perspective on the dynamic landscape of MEMS sensor technology. From Bosch’s evolution to a solutions provider with a focus on sustainability and market-driven innovations, Finkbeiner offered a deep dive into how Bosch Sensortec is positioning itself at the forefront of the industry. “We have to think in terms of the end application and determine what the right hardware and software configuration should be in order to provide solutions with the greatest benefit and flexibility.”Further insights into the future of MEMS and sensor technology will be shared by Finkbeiner during his keynote at the SEMI MEMS Imaging Sensors Summit on November 14, 2024, in Munich, Germany. Registration is still open.SEMI: Welcome, Stefan, and thank you for sharing your insights on advanced sensor technologies. Let’s start with a personal question: What motivates and inspires you about working in sensor technology?Finkbeiner: Sensor technology is very diverse and has significant impacts on consumers. We take pride in prioritizing consumers’ needs and benefits. True to the Bosch motto, “Invented for life,” we are committed to making life better, easier and healthier. This is demonstrated in our sensing solutions, which provide valuable data for fitness tracking in smartwatches, enhance the audio experience in hearables, and enable real-time monitoring of air quality to help individuals make informed decisions for a healthier environment. I am fascinated by technology advancements that are enabling the scaling of sensors—and the processing power and intelligence packed into these increasingly compact devices. For instance, our latest acceleration sensors for hearables are the smallest in the world and are nearly invisible at just 1.2 x 0.8 x 0.55 mm³.We leverage innovative wafer level chip scale packaging (WLCSP) to achieve this reduced form factor. These compact, feature-rich, high-performance accelerometers are easier to integrate in the latest generation consumer products where size and functionality are critical requirements.SEMI: How has Bosch Sensortec’s approach evolved over the years and what is the company’s primary focus today? Finkbeiner: We began our success story a few years ago as a hardware supplier, with one of our first applications being the 'Portrait-Landscape' function in smartphones. Over time, we’ve evolved into one of the leading providers of MEMS sensors.Today, we no longer see ourselves purely as a sensor manufacturer, but as a technology solutions provider. Our focus has shifted to think in terms of the end application and determine what the right hardware and software configuration should be to provide solutions with the greatest benefit and flexibility.Achieving this requires significant software and artificial intelligence (AI) development. In essence, we are optimizing software through self-learning models. Hardware remains essential for optimizing power consumption, with most sensors integrating a controller alongside the ASIC to enable seamless software integration.This unique software and hardware configuration unlocks exciting possibilities and broadens our market reach. We see significant growth in head-mounted devices, and we are actively working on related acoustics solutions.SEMI: Looking ahead, what trends do you anticipate will have the most significant impact on the MEMS sensors market?Finkbeiner: We see several trends that will significantly impact the MEMS sensor market. First, there is growing demand for personal health monitoring in consumer and mobile electronics. Wearable devices, in particular, are becoming essential tools for individuals to track their health and fitness status. This trend requires MEMS sensors to become even more accurate, with solutions that include sophisticated software algorithms to ensure reliability, accuracy, and reproducibility. As a result, AI and machine learning (ML) technologies will play a crucial role in enhancing sensor performance.A second important trend is the continued miniaturization of MEMS sensors. To meet customer demands, sensors must integrate more functionality, including edge-processing capabilities. For example, what once may have been a simple accelerometer with a step-counting algorithm is now evolving into a 6-axis Inertial Measurement Unit (IMU) with an integrated microcontroller and advanced AI/ML software. A great example of this is in True Wireless Stereo (TWS) earphones, where the IMU not only tracks steps but also enables complex tasks like dead reckoning and supports 3D audio—all within the tight constraints of a small TWS earbud housing. Low power consumption, as always, is a critical factor for these mobile devices to meet CE (Conformité Européenne) standards.Finally, we believe that smart glasses, augmented reality (AR) and virtual reality (VR) devices are poised to become the “next big thing.” These devices require advanced image projection optics that offer excellent optical quality, low weight, and ease of use to ensure consumer adoption. We believe our MEMS-based LBS (Laser Beam Scanning) solution is ideal for these applications. Additionally, the successful adoption of smart glasses hinges on high-performance MEMS sensors that are compact, accurate, and power-efficient—critical requirements for all-day wearability and functionality.These trends underscore the need for MEMS technology to evolve, integrating greater functionality, precision, and efficiency to meet the demands of next-generation consumer devices.SEMI: What are some of the biggest challenges facing the MEMS sensors industry today, and how can companies overcome them?Finkbeiner: One key challenge is that the smartphone market—arguably the most attractive market for a variety of MEMS and MOEMS sensors—has become more or less saturated. To stay competitive, MEMS companies must innovate existing products while also developing new, differentiated sensors and actuators for next-generation mobile products.SEMI: How is Bosch Sensortec supporting sustainability initiatives?Finkbeiner: We are helping to mitigate climate change with our low carbon footprint solutions.Up to 20% of annual global carbon emissions are caused by forest fires. This is equivalent to carbon dioxide emitted by all the vehicles driven worldwide. Our sensors can detect forest fires before they develop into wildfires by measuring various gases such as carbon monoxide and hydrogen. In parallel, we are working with our production partners to reduce our carbon footprint over the coming years, while also replacing or minimizing the use of environmentally hazardous chemicals, such as PFAS.SEMI: What are you most excited about for the MEMS Imaging Sensors Summit, and how do you think it will impact the European semiconductor industry?Finkbeiner: The European semiconductor industry has deep expertise in MEMS and sensor technologies, positioning it to make a significant impact in markets such as consumer health, optical sensing, and AR displays. By continuing to focus on sustainable solutions, we can drive even greater impact for the broader industry and secure Europe’s leadership in these growth sectors.I look forward to collaborating with industry peers at the Summit to define next steps needed to advance Europe’s leadership. The MEMS Summit is an invaluable opportunity to collaborate and drive progress, and I warmly invite my colleagues to join us in shaping the future of the European semiconductor industry.Dr. Stefan Finkbeiner Dr. Stefan Finkbeiner has been CEO and General Manager at Bosch Sensortec GmbH since 2012. He was born in 1966 in Freudenstadt, Germany. Stefan Finkbeiner held various senior positions at Bosch including Director of Sensor Marketing, Director of Corporate Research in microsystems technology, and Vice President of Sensor Engineering. He looks back on almost 30 years in semiconductor industry working in different positions related to sensor research, development, manufacturing, and marketing. Due to his wide experience in semiconductor and sensor industry, Stefan Finkbeiner is a recognized guest in panel discussions and as keynote speaker. SEMI ContactSitong He / Communications Manager, SEMI EuropeEmail: [email protected]: +49 151 5546 2638

In today’s rapidly evolving semiconductor industry, ensuring both precision and efficiency in manufacturing has become an increasing challenge, particularly as advanced technologies like MEMS and AI chips push the boundaries of design and production. Inspection methods that were once sufficient are now falling short, making room for cutting-edge solutions powered by artificial intelligence (AI). The introduction of AI-driven 3D X-ray inspection technologies is transforming the landscape, offering manufacturers a sophisticated tool to ensure quality control, while driving sustainable production strategies.SEMI spoke with, Joscha Malin, Product Manager, and Daniel Stickler, R D Expert for X-ray Imaging at Comet AG, Industrial X-Ray System Division, to explore how AI-powered 3D X-ray inspection technologies are shaping manufacturing. They delve into how these technologies address critical challenges during inspections and defect analysis, using tools such as Dragonfly 3D World software for user-friendly, AI-driven insights that facilitate effective decision-making.Further insights into the application of AI-powered 3D X-ray inspection technologies and their role in advancing MEMS manufacturing will be presented by Stickler at the SEMI MEMS Imaging Sensors Summit on November 14, 2024, in Munich, Germany. Registration is now open.SEMI: Thank you both for agreeing to share your insights. To start, can you explain the importance of inspection strategies in the context of MEMS manufacturing?Malin: As MEMS devices become increasingly miniaturized and complex, effective inspection strategies are crucial. These strategies not only accelerate the wrap-up of production processes, but also significantly enhance product yield. With tighter tolerances and various materials involved, ensuring the integrity and functionality of each component is more critical than ever. A robust inspection strategy allows us to catch potential defects early, which can save time and costs associated with rework or scrap.Stickler: The evolution of MEMS technology, particularly in AI chips, demands a higher level of inspection sophistication. Traditional methods may fall short in providing the necessary detail and speed, which is why we’re focusing on advanced solutions like our AI-powered 3D X-ray inspection.SEMI: Could you elaborate on how the 3D X-ray technology differs from conventional inspection methods? Stickler: The 3D X-ray technology we utilize acts as a bridge between traditional optical methods and standard 2D X-ray inspection. It offers high-resolution, three-dimensional images without damaging the samples. 3D X-ray technology emphasizes three main benefits: clarity, efficiency, and actionable insights. This means we can obtain detailed images that help us analyze components more effectively, allowing for real-time decision-making.Malin: Moreover, the clarity and detail provided by the 3D X-ray images are critical when it comes to defect analysis in MEMS devices. They allow us to assess mechanical, electrical, and assembly errors in ways that conventional methods simply cannot. This leads to a more reliable production process.SEMI: What specific MEMS defects can be effectively analyzed using this technology?Stickler: There are several types of defects we can analyze. For instance, we can detect mechanical defects such as stiction or fractures, as well as electrical failures like short circuits. The 3D X-ray inspection allows us to visualize these defects in detail. Additionally, we can monitor assembly errors, which are particularly important in complex MEMS devices where misalignments can lead to significant issues.Malin: I’d like to add that early detection of these defects is paramount. The faster we identify issues, the quicker we can implement corrective actions, thereby improving overall yield and reducing production costs.SEMI: You mentioned yield improvement earlier. Can you explain how your technology contributes to that?Malin: Our approach supports process optimization by providing information on product characteristics and, for example, allows us to identify trends early on that may lead to yield issues later. We also aim to accelerate new product introduction in the early phase by rapid feedback, saving time and cost. This is crucial because many defects may not be apparent until later stages of production. With our technology, we can monitor samples in real-time, allowing us to react promptly to emerging challenges.Stickler: By integrating this feedback loop, we can significantly shorten the time to market for new products. This is particularly beneficial in industries where speed and efficiency are essential.SEMI: Can you tell us about Dragonfly 3D World software and its role in this process?Malin: Dragonfly 3D World is a user-friendly software that leverages AI and, specifically, deep learning for image processing. It enables users to efficiently perform bump metrology and defect identification, for example, without needing extensive expertise in the field. The software makes complex processes manageable, even for operators who may not be specialists in image processing.Stickler: Beside MEMS and advanced packaging in GPU production, this software is indeed an “AI-for-AI” application. By utilizing deep learning, users can train models that adapt to various imaging tasks, making the entire inspection process more efficient. The insights generated from the 3D X-ray images are automated, enhancing usability and streamlining workflows.SEMI: In conclusion, what are the key takeaways you’d like to share?Malin: The key takeaways are that AI-driven 3D X-ray inspection is transformative for the MEMS manufacturing process, enhancing inspection strategies and defect detection significantly. By integrating advanced technologies, we can ensure higher product quality and efficiency.Stickler: Yes, and I would emphasize the importance of powerful monitoring and non-destructive test tools. Our innovative solutions not only improve yield, but also pave the way for sustainable practices in manufacturing, ultimately benefiting the industry. Dr. Daniel SticklerDirector X-ray Technology Components at Comet AG, Industrial X-Ray System Division. Based in Hamburg, Germany, he holds a PhD in Physics from the University of Hamburg and has extensive experience in X-ray imaging, semiconductor X-ray applications and product innovations. Joscha MalinDirector Product Marketing Software Products at Comet AG, Industrial X-Ray System Division. Based in Hamburg, Germany, he holds a degree in Electrical Engineering with specialization in Semiconductors and profound experience in the industry. For over a decade, he has focused on developing X-ray inspection and metrology solutions, especially for the Semiconductor industry. SEMI ContactSitong He / Communications Manager, SEMI EuropeEmail: [email protected]: +49 151 5546 2638

In the rapidly-evolving semiconductor industry, maintaining a competitive edge is crucial. To position Europe at the forefront of global semiconductor innovation, imec is leading the NanoIC pilot line initiative. Aligned with the European Chips Act, this initiative is a strategic move to bolster Europe's leadership in key markets like high performance computing, automotive, and healthcare.SEMI spoke with Srikanth Samavedam and Jo De Boeck from imec, Belgium, to learn more about the NanoIC pilot line and to better understand its goals, challenges, and prospects. From transitioning to gate-all-around (GAA) nanosheet devices, to developing advanced memory technologies and interconnects, this conversation highlights the cutting-edge advancements made possible through collaboration across the industry’s value chain.SEMI: How is the NanoIC pilot line working to revolutionize the semiconductor industry, and what are its main objectives?Samavedam: The NanoIC pilot line is a European initiative aimed at bridging the gap between R D and industrial innovation. The project is creating a beyond-2nm system-on-chip (SoC) pilot line, developing advanced logic, memory, and interconnect technologies. This effort supports the European Chips Act's vision for leadership and competitiveness in global semiconductor innovation, particularly in critical markets like high performance computing, communication, automotive, energy, and healthcare. However, advanced technologies come with more complexity, and addressing these complexity challenges requires more mature module baseline flows. By improving baseline flow repeatability and variability while reducing defectivity, we can accelerate the development of future technologies. The NanoIC pilot line is working to provide access to these advanced technologies and baselines to develop future compute systems. This will help ensure European competitiveness across the industry – from semiconductor materials, equipment and design to systems and applications.SEMI: Who are the core partners involved in this initiative?De Boeck: Key partners of the pilot line include CEA-Leti, Fraunhofer-Gesellschaft, VTT Technical Research Centre of Finland, Tyndall National Institute, and the Center for Surface Science and Nanotechnology of the University POLITEHNICA of Bucharest. This project is also supported by the Flemish government, other participating states, and the Chips Joint Undertaking of the EU Chips Act.These institutions and organizations bring a wealth of knowledge and resources, and imec compliments their efforts by providing access to its global partnerships with key industry leaders. The NanoIC pilot line is helping strengthen Europe’s global semiconductor industry leadership while aligning efforts with other regional Chips Acts. SEMI: Can you elaborate on the significance of transitioning from field-effect transistors (FinFETs) transistors to GAA nanosheet devices in CMOS technology?Samavedam: The transition from FinFETs to GAA nanosheet devices is a significant advancement in CMOS device technology. FinFETs have been the backbone of CMOS technology from the 22nm to the 3nm node. But starting at the 2nm node, nanosheet devices will need to be introduced. Nanosheet devices, including variants like Forksheet devices, are expected to drive scaling and performance through three generations – 2nm, A14, and A10. Complementary FET (CFET) architectures are also expected to be introduced around 2031 at the A7 node, which will represent another major inflection point in CMOS device design. This progression requires extensive research into new materials, process modules, equipment, and advanced patterning capabilities using high numerical aperture extreme ultraviolet (high NA EUV) lithography – all of which will be implemented on the NanoIC pilot line. FIGURE PROVIDED BY IMEC │ SCHEMATIC ILLUSTRATION OF A FUTURE COMPUTE SYSTEM. THE SYSTEM IS MADE OF LARGE MULTI-DIE ELECTRICAL-OPTICAL INTERPOSER PROVIDING ELECTRICAL AND OPTICAL INTERCONNECTS BETWEEN THE VARIOUS CHIPLETS (CPUS, GPUS, HBM). ALSO SHOWN ARE CONNECTIONS TO PACKAGE SUBSTRATE, AS WELL AS FIBER CONNECTORS AND AN INTEGRATED LASER SOURCE. CENTRAL PROCESSING UNIT (CPU); GRAPHICS PROCESSING UNIT (GPU); HIGH BANDWITH MEMORY (HBM); PROCESSING UNIT THAT CAN INCLUDE CPUS, GPUS, AND OTHER SPECIALIZED PROCESSORS (XPU); APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC); ELECTRONIC INTEGRATED CIRCUIT (EIC); FF-LEVEL: FEMTOFARAD-LEVEL; FIELD-PROGRAMMABLE GATE ARRAY (FGPA); GAAS QD: GALLIUM ARSENIDE QUANTUM DOT; INTEGRATED SILICON PHOTONICS PLATFORM 300MM (ISIPP300); REDISTRIBUTION LAYER (RDL); SILICON PHOTONICS (SIPHO); THROUGH PACKAGE VIA (TPV). SEMI: What are the key innovations necessary for advancing memory technology?Samavedam: As SRAM scaling slows, the exploration of novel, dense embedded memory concepts will become imperative. Technologies like spin orbit torque magnetic RAM (SOT-MRAM) and 2-transistor 0-capacitor (2T0C) embedded DRAM using deposited semiconductors like indium gallium zinc oxide (IGZO) are promising. These innovations address memory capacity and bandwidth challenges from new workloads in compute systems. Additionally, developing a 3D memory platform to explore future memory options will be essential for improving SRAM and DRAM. These advancements will help meet the demands of new applications like machine learning, augmented and virtual reality, and autonomous vehicles.SEMI: How do advanced interconnect technologies contribute to the future of semiconductor design?Samavedam: Advanced interconnect technologies, like chip-to-chip lateral (2.5D or interposer technologies) and vertical interconnects (3D technologies), play a crucial role in addressing memory capacity and bandwidth challenges. These technologies enable the partitioning of SoC functions into separate dies, allowing for more efficient and scalable designs. Advances like pitch scaling of micro-bumps and copper (Cu) hybrid bonding are facilitating this fine-grained partitioning of SoC functions. Additionally, optical interconnects and 3D interconnect-enabled co-packaging provide high-bandwidth and low-power connectivity at wafer scale. The rise of chiplet architectures and standardization will also increase the demand for low-cost, tight-pitch interconnect technologies like Cu/polymer redistribution layers.SEMI: How do your collaborators benefit from the NanoIC pilot line? De Boeck: One of the biggest collaborator benefits is the pilot line’s commitment to knowledge sharing through R D access and training. We invite foundries, IDMs, materials suppliers, equipment suppliers, and system companies/OEMs to jointly develop the materials, process modules, and integration flows to accelerate the development of beyond-2nm SoC technology pillars.Design pathfinding and system exploration process design kits (PDKs) will be available for start-ups, small- and medium enterprises, universities, and design and system companies to aid in prototyping and testing their designs. The NanoIC pilot line will also offer comprehensive training programs, including virtual PDK training, bootcamps for faculty, and internships and expert courses for students. To learn more, experts and key partners of the NanoIC pilot line will be presenting from 14 -16:40 at SEMICON Europa on November 12. imec’s program, ITF Chip into the Future, will highlight advancements in digital technology, capacity building through the European Chips Act, and the role of the NanoIC pilot line in accelerating beyond-2nm innovation. The conversation will also address industry requirements for pilot lines, emerging initiatives boosting Europe’s innovation and competitiveness, and perspectives on advanced materials and semiconductor equipment. Srikanth Samavedam, Senior Vice President of Semiconductor Technologies at imec, oversees programs in logic, memory, photonics, and 3D integration. Previously, he was a senior director at GlobalFoundries, leading 14nm FinFET technology into production and developing 7nm CMOS. Starting his career at Motorola, he worked on strained silicon and other advanced materials. He holds a Ph.D. in materials science and engineering from MIT and a master's degree from Purdue University. Jo De Boeck, Executive Vice President and Chief Strategy Officer at imec, oversees the company’s strategic direction and serves on its executive board. He joined imec in 1991 after earning his Ph.D. from KU Leuven and has since held various leadership roles, including head of imec’s Smart Systems and Energy Technology business unit and CTO. De Boeck is also a part-time professor at KU Leuven. Maria Daniela Perez / Communications Manager, SEMI EuropePhone: +49 160 2562977Email: [email protected]

With the rapid proliferation of electronics applications with more powerful embedded intelligence, demand for smarter, more efficient sensors is increasing to help devices connect to the world around them. As the semiconductor industry drives the future of connected technologies and sustainable solutions, it faces challenges in energy consumption, resource management, and ensuring data security.SEMI spoke with Simone Ferri, Vice President and General Manager at STMicroelectronics (ST), about current trends and challenges in the Micro-electromechanical Systems (MEMS) and imaging sensors market and how ST is driving innovation in this rapidly evolving industry. Ferri shared insights ahead of his keynote presentation at the SEMI MEMS Imaging Sensors Summit on November 14, 2024, in Munich. Registration is open.SEMI: Welcome, Simone, and thank you for sharing your perspective on the dynamics and trends for today’s MEMS and imaging sensors. To start, how would you describe the current market dynamics for these technologies, and what key factors are influencing these dynamics? Ferri: Right now, the MEMS and imaging sensors market is primarily driven by applications such as automotive electronics, consumer medical devices, AI-powered devices, and intelligent wake-up systems.According to Omdia, the MEMS market is projected to reach approximately $11 billion by 2027, with a CAGR of 2.8% from 2022 and 2027. Currently, automotive applications account for 50% of this market, with industrial at 15% and consumer at 35%. Notably, the automotive sector is the fastest growing, with a 5.4% CAGR, driven by the increasing use of inertial measurement units (IMUs) and microphones.In addition, Yole Group estimates that the imaging market, including optical sensing, will grow at a 4.7% CAGR between 2023 and 2029. Although mobile phone applications remain the primary driver of Complementary Metal-Oxide-Semiconductor (CMOS) image sensors (CIS) volumes, other sectors, including consumer electronics, automotive, and security imaging, are also contributing to the growth.Long-term forecasts for smartphone sales have been trending downwards, but mobile phones still remain a major driver of applications, innovation, and overall volume in the imaging market. Notably, the automotive imaging sector is one of the fastest growing markets and is expected to drive additional demand for CIS.Factors that influence the current market include global economic conditions, regulatory changes, geopolitical factors, technological innovations, and the emergence of new applications and use cases.SEMI: Can you elaborate on the growth strategies that STMicroelectronics is adopting to stay competitive in the MEMS and imaging sensors market? Ferri: ST has played a pivotal role in both the MEMS and imaging sensors markets for over two decades with its proprietary silicon technologies. We fully leverage our Integrated Device Manufacturer (IDM) business model, which allows us to support our customers through integrated capabilities for both design and manufacturing.To remain competitive, we are exploring new markets for MEMS sensors, particularly in digital healthcare with biosensors, where wearable devices are expected to exceed 500 million units per year by 2027.We’re focusing on the growing demand for automotive sensors such as accelerometers, Inertial Measurement Units (IMU), and pressure sensors, particularly with the rise of electric vehicles. We are enhancing the integration and synergy between automotive and personal devices. For example, we are combining high-g and low-g accelerometers within a single IMU, enabling accurate fall and crash detection, along with precise orientation and wake-up functionality.AI is another one of our priorities. In today's digitalized world, AI enables real-time, contextual understanding and the ability to make decisions that optimize and reduce the power consumption of the final device. Sensors are no longer merely for data collection. Thanks to AI, sensors can interact with their environment and significantly contribute to innovation and sustainability.We are also prioritizing low power consumption. Our MEMS technology operates in low-power mode with almost negligible energy use, activating only when necessary, without waking up the system to understand its environment or to be reconfigured.In addition, we’ve seen optical sensing continue to grow year over year. Optical sensing now offers features such as 3D capture, low-power and low-footprint computer vision, Near InfraRed (NIR) and even Short Wavelength InfraRed (SWIR).We are accelerating and leveraging our IDM model and broadband semiconductor supplier positioning to propose wider system offerings based on the array of sensors and microprocessors that ST develops. As the world shifts toward widespread use of sensors and data collection, the demand for secure sensing technologies is growing, extending beyond mobile and PC applications to spatial computing and AR/VR environments. For example, if we are talking about recognizing specific persons in an AR environment, we don't want the data related to these persons to be sent to the cloud before a decision is made about whether they are supposed to be there or not, as such information can be intercepted. We want all the data to be managed at sensor level and only a warning of rejection or acceptance to be transferred outside our secure sensor. SEMI: What are some of the latest technological innovations in MEMS and imaging sensors that are shaping the industry? Ferri: In MEMS, we're seeing significant advancements in three key areas:- In-sensor AI is integrating technologies in the sensors such as machine learning core (MLC), adaptive self-configuration (ASC), and intelligent sensor processing units (ISPU).- Open sensors are designed to interface seamlessly with other sensors, allowing third parties to benefit from on-sensor processing innovations, while building an ecosystem to create joint value with customers.- Accurate sensors are providing high-precision data, enabling better decision-making and smoother, more natural user interactions. These sensors also reduce factory calibration time and resources, leading to overall lower energy consumption. Because of their accuracy, onboard MLC, and ASC, the sensors can also reconfigure themselves without interaction with the processor, thus guaranteeing the proper accuracy at lower power consumption, at any time, under any condition.In the imaging sensor market, key trends include:- Higher Pixel performance is leading to improved signal-to-noise ratio (SNR), low light performance, better quantum efficiency (QE) and lower noise performance. Despite post processing, pixel performance remains the key factor as SNR performance must remain high while the pixel shrink roadmap advances.- Embedded Intelligence is providing local processing for local decision making, enhanced security, advanced image sensor processing (ISP) for improved image quality, and fusing sensor functions to deliver a better user-experience.- "Always on" capabilities are supporting mass sensorization and deployment of optical sensing solutions everywhere through specific low-power design techniques, process development, and overall system architecture optimization.SEMI: Looking toward the future, what trends do you anticipate will have the most significant impact on the MEMS and imaging sensors market? Ferri: Some macrotrends for sensors include:Electrification: Certain consumer and industrial applications are now being adopted in the automotive sector, especially with the rise of electric vehicles creating new opportunities for innovation and for new players to enter the market. As example, the predictive maintenance that has been developed for industrial electric motors is ported 1:1 to electric vehicles.AI: Regarding data transmission, distributed architecture will push AI towards edge computing, increasingly supported by advancements in 6G and foldable technologies. Additionally, as AI becomes more integrated, the maintenance and security for AI will require more attention.Smart home, buildings, and cities: As cities grow, the demand for smart homes and buildings rises, requiring more sensors to manage energy, security, and urban infrastructure efficiently. Over 55% of the global population and 70% of the EU population reside in cities. Urban areas generate more than 80% of the world’s GDP, and by 2030, it's anticipated that 68% of the global population will be urban dwellers, pointing to the growing need for smart cities.Aging population and digital health: The integration of biosensors with MEMS technology will be crucial for addressing the needs of an aging population.Overall, the use of image sensors for environmental sensing is steadily increasing. This is a major focus for ST, particularly in 3D sensing. New use cases, such as presence detection, are enhancing security and reducing power consumption due to efficient data processing. Additionally, the average number of cameras in smartphones, automobiles, and even in devices like robots and vacuum cleaners, continues to grow.SEMI: What has STMicroelectronics been working on, and what are your plans for the upcoming years? Ferri: To date, we have shipped over 23 billion MEMS sensors. Still, we remain committed to continuously improving our products and enhancing our MEMS technology in terms of affordability, miniaturization, performance, and novelty. We are striving to set the stage for a future defined by innovation and excellence with:Evolution of our current product portfolio by investing in lower power consumption, lower supply voltage, and additional and more sophisticated in-sensor AI for an effective distributed AI conceptNew sensors for presence detection, like infrared (IR) sensors, and health-focused sensors such as biosensors.MEMS sensors are also becoming increasingly accurate, open towards different ecosystems of technologies, and so intelligent that they can self-configure and reduce power consumption thanks to optimal data processing. These attributes allow us to provide meaningful and sustainable solutions across sectors such as automotive, industrial, infrastructure, and personal electronics, enabling us to improve energy efficiency, reduce waste, and support sustainable practices for a greener planet.For the past 10 years, ST has focused on depth sensing across multiple use cases. Today, ST is the number one in the world for time-of-flight solutions through our ST FlightSense product family. More recently, we launched our global shutter image sensors family, ST BrightSense, to address markets like personal electronics, automotive, industrial, communications equipment, and computers and peripherals.More specifically on the automotive side, we have the portfolio, customers, and customer program awards to lead the driver and occupancy monitoring market. We continue to secure design wins from our growing customer base while we expand our product portfolio and broaden our customer and application footprints.SEMI: What are some of the biggest challenges facing the MEMS and imaging sensors industry today, and how is ST addressing them? Ferri: The MEMS and imaging sensors industry faces several challenges, but with strategic planning and innovative solutions, companies can overcome these obstacles by focusing on the following:Integration: With our biosensors, we are doing more with less space. For example, in a standard accelerometer, we integrate an analog front end for electrocardiogram (ECG) analysis, enhancing functionality without increasing the device footprint.Performance enhancement: Ensuring high performance and reliability in various environmental conditions is crucial, especially in automotive and healthcare applications. To meet these demands, we deploy comprehensive testing protocols to ensure our sensors meet performance and reliability standards.Power efficiency: Reducing power consumption is vital, particularly for battery-operated devices like smartphones and IoT devices. We are developing low-power architectures to address this need.Data security: With the growing use of imaging sensors in surveillance and personal devices, data security and privacy have become paramount. Our solutions include encryption for data transmission and storage, as well as robust access control mechanisms to prevent unauthorized access to sensor data.Additionally, supply chain issues remain a significant challenge today. We believe our strategy and capacity as an IDM, combined with our strong innovation capabilities, give us a competitive edge in supply chain management.SEMI: What are you most looking forward to at the MEMS Imaging Sensors Summit, and what does it mean for the European semiconductor industry? Ferri: I look forward to the Summit as a valuable opportunity to connect with industry peers, share insights, and explore new collaborations. I encourage my peers to attend, as it’s a unique platform to collectively shape the future of our industry and sustain Europe’s leadership in semiconductor innovation. About Simone FerriSimone Ferri is Vice President of APMS Group and General Manager for MEMS sub-group at STMicroelectronics. Ferri began his career in STMicroelectronics in 1999 as an R D engineer before becoming a digital designer for the company’s audio division, leading into product management after 5 years. In 2014, ST entrusted Ferri with MEMS consumer sensors followed by global MEMS-sensor related Marketing and Application activities across all markets and segments, leading into his current role. Ferri graduated with a degree in microelectronics from Politecnico di Milano (Polytechnic of Milan), where he also completed his MBA. Sitong He is Marketing and Communications Manager at SEMI Europe.

Verific Design Automation is an electronic design automation (EDA) developer of front-end software and a member of the Electronic System Design (ESD) Alliance. Verific is also viewed as a valued supplier to many EDA, field-programmable gate array (FPGA) and semiconductor companies –– some still around, some acquired by larger EDA companies, and some long gone –– for the past 25 years. With this backdrop, Bob Smith, executive director of the ESD Alliance, talks with Rob Dekker, Verific’s founder, president, and CTO, and Michiel Ligthart, its COO, about the evolution of the company and the industry over the last 25 years, the emerging EDA products space and what’s to come. Smith: This is the 25th anniversary of the founding of Verific. How did it get started? Dekker: The company I worked for before I started Verific was Exemplar Logic (now Siemens EDA), founded by Ewald Detjens in the 1990s. Exemplar started off making an RTL-to-Xilinx FPGAs path using the VHDL hardware description language (HDL) as the entry language. I worked on the VHDL language parser. As I was doing that work, I looked at the VHDL language reference manual and made sure that all the code complied with the rules set by the IEEE standards committee. I wondered why I was doing it for just one company, because it was and still is an IEEE standard language. Every tool vendor that wants to support VHDL would have someone like me looking at the language reference manual and building a language front-end that complies with all the rules in the standard. As I gained experience and finally left Exemplar, I already knew how to make a language front-end and started building a good one for the Verilog HDL. The initial idea was not to sell it to different companies but to build an equivalence checker formal verification tool that could be installed on every designer’s desktop, where they could check their designs at various stages in the design flow. I needed funding, and started selling the language front-end thinking that no one should have to rewrite a language front-end because it's already a standard. That's when the idea came to start Verific. I wanted to build a standard language front-end, with the possibility of creating a formal tool based on that front-end. The language front-end was popular among various EDA tool vendors and startup companies. Formal tools, synthesis tools, simulators or virtual prototyping tools, emulators, and so on all need a language front-end. I was starting to license the front-end and got so busy that I asked my good friend Michiel to run the business so I could focus on the technical side. After that, we started to grow, acquired an exceptional team in India run by my friend Abhijit Chakrabarty, and hired Rick Carlson as VP of sales. It quickly became a real company, and we started to license the language front-ends to the entire EDA industry. One company wanted to license our language front-end to build an equivalence checker. At that point, we had to decide whether to stay in the language front-end business or to make an equivalence checker and compete with our customers. We decided that competing was not a good idea and chose to focus on language front-end for the EDA industry. We have been doing this ever since for most EDA tools, from startup companies, all the way to large semiconductor companies. Their tools have been built with a language front-end developed at Verific, and we are proud of that. Smith: What have you seen change since you started? Have you seen any big changes that surprised you as the industry has evolved? Dekker: I wouldn't say big changes overall, but I've been impressed by the amount of innovation in the EDA industry. The industry is dynamic, with new tool vendors coming up and good ideas being explored. We are in a wonderful industry that is vibrant with innovation and talented people. This is what impressed me about the industry initially, and it still does. At Verific, we want to be an incubator for new innovations to flourish in an EDA industry dominated by a small number of large players. Ligthart: One change that had a significant impact on Verific specifically is the introduction of SystemVerilog. When Rob started out, there was Verilog 95 and VHDL. Verilog 95 was a relatively simple language. VHDL was complicated. We saw that early customers often wrote their own Verilog parser and came to Rob for the VHDL parser. In 2005, the IEEE 1800, also known as SystemVerilog, was introduced. That was a game changer, because suddenly, adopting SystemVerilog in the Verilog customer base required a new front-end that was as difficult to create as writing VHDL parsers. That was an inflection point for the company, and it started to grow. Before then, it was a nice company. After 2005, it became a growth company. Nowadays, we equally support SystemVerilog and VHDL. They're both complicated languages. People for the past 20 years have proclaimed the death of VHDL. It did not happen and will not happen. The two languages go hand in hand in different parts of the world. Most EDA companies support both because their end users require both. Smith: Verific coined the term “bespoke EDA.” How do you define it? Ligthart: For that, we need a bit of history. Fifty years ago, semiconductor companies started to write their own software tools to design their semiconductors. Those days, it was still called CAD, computer-aided design. Over time, we saw the introduction of EDA companies that tackled singular problems like simulation, place and route, or logic synthesis, and they started replacing in-house developed tools. In the past seven years, many of the larger semiconductor companies and system companies have started to develop in-house EDA tools again. Of course, they still license most of their design tools from EDA companies, but for certain design aspects, they develop their own design flow. They write their own internal EDA tools that are specific to that company, and they don’t go outside of that company. That's what we call “bespoke EDA.” Smith: These chip companies can afford to do this? Ligthart: Yes, because they are large enough and have the people to do it. They license their SystemVerilog and VHDL front-ends from us, so they do not have to invest five years of development for that piece of their flow. They take our parsers and elaborators and build something of their own — bespoke for their semiconductor design flow. Smith: It makes me think of Google, Meta. Ligthart: Let me put it this way. Of the magnificent seven technology stocks, six have a Verific license. Smith: How do you see AI changing EDA design tools? How will AI impact you? Dekker: This question about AI is coming up quite a bit, and I have a more conservative opinion. I don't know if AI is going to change EDA tools by themselves. EDA tools are highly optimized to do a particular task, it would be difficult for AI to beat that. If it did, it would surprise me. Outside of tools, like the design exploration phase for example, I think AI might make a humongous difference. AI could make it much quicker to explore different design alternatives. Right now, several AI-based companies are engaging with Verific, and they provide the design environment to do optimizations. AI could also help engineers improve their work. This would be more at the micro level, where individual engineers use ChatGPT type of engines and language models to enhance their programming styles, algorithms, and implementations. At the micro level, I think AI has an impact. At the macro level outside of the tools, I think AI will also have an impact. I doubt AI will change anything with the tools themselves. Ligthart: I'm pretty much in line with everything Rob said. At the Design Automation Conference (DAC), we showcased our relationship with four EDA startups that are applying or are in the process of applying artificial intelligence to their design objectives. As Rob said, the first step is getting a Verific license so that they have SystemVerilog already in place. Then, they apply AI-based algorithms to tackle certain aspects of the semiconductor design cycle. In terms of how successful they are, that's up to them to prove, but we have a front-row seat to watch their progression and success. Smith: What trends in the industry are you seeing? Dekker: Niels Bohr, a renowned physicist of the 20th century, once said, "prediction is very difficult, especially if it's about the future." Our EDA industry is vibrant, and it’s hard to see where it's going. I think that the EDA industry is here to stay. EDA companies are becoming more and more popular in the stock market. This industry is 40 years old, but it’s still dynamic and still full of innovation. It's extremely important that we keep this industry open, that we share ideas with each other, and that we provide solutions for the increasing complexity of chip and system designs, especially as AI gains prominence. The industry will change, and as it changes, the requirements for EDA tools will also need to be adjusted and there's a range of directions that our industry can go in. Verific is here to support that. About Rob Dekker Rob Dekker is president, founder, CTO and principal developer of Verific’s HDL source code software. Prior to founding Verific, Dekker was a software developer, manager, and director at Exemplar Logic, where he was the architect and a primary developer of Leonardo. Dekker started his career with Philips Research in the Netherlands, where he worked on the testability of VLSI circuits. He graduated from Delft University of Technology, the Netherlands, with a Master of Science degree in electrical engineering. About Michiel LigthartMichiel Ligthart is Verific’s COO and has an extensive background in engineering, product marketing, and general management. Prior to Verific, Ligthart was vice president and general manager of west coast operations for Theseus Logic, a startup in asynchronous logic. Previously, he spent eight years with Exemplar Logic in engineering and marketing roles. Ligthart started his career with Philips Research Labs and was a visiting scholar at the Center for Integrated Systems at Stanford University. He has a Master of Science degree in electrical engineering from Delft University of Technology, the Netherlands. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

The drive to scale nodes towards physical limits, known as "More than Moore," and the adoption of 3D architecture in chip integration strategies for advanced logic and memory applications has led to unprecedented demand for high-quality dependable materials solutions. With the aid of digital solutions, the process is expedited with higher quality and efficiency.SEMI spoke with Thorsten vom Stein, Director, Head of Process Design Semiconductor Materials at Merck KGaA, Darmstadt, Germany, about how materials innovations and advanced packaging can contribute to smarter supply chain solutions for a sustainable ecosystem.More insights into key aspects of 3D architecture in chip integration and heterogeneous integration will be shared at the Advanced Packaging Conference (APC) during SEMICON Europa 2024, Nov. 12-15 in Munich, Germany. Registration is open.SEMI: What makes the digitalization of chemical process design for semiconductor materials manufacturing so challenging at a technology level? Vom Stein: The primary challenge in digitalization of process design is achieving data rich experimentation and design flexibility from the start. When we begin the process design for a novel material solution, the freedom of design needs to be very high for optimal outcomes. For example, to identify the best sequence of unit operations to achieve best process intensification, do we need a distillation or extraction after the reaction to meet the purity requirements? At the same time, the samples from these early process trials need to have purity levels and process reliability standards for high-volume manufacturing of routine production in order to meet the requirements of our customers’ leading-edge chip integration strategies. We address this need by executing data rich experimentation starting with first trial, and thereby establish “production ready” data density in the lab.To avoid confining our design space, we therefore need highly “sensorized” and automated modular lab equipment that can give us the data density we need and flexibility at the same time.SEMI: Are data-driven approaches also applied to streamline manufacturing processes? Vom Stein: Yes, data-driven approaches are key to driving cost, quality, process reliability and sustainable excellence. As we scale up from lab experiments to high-volume manufacturing—often times increasing volumes by two or three orders of magnitude—we scale the process model virtually ahead of its physical twin to de-risk these major scale-up steps. An example of this is simulating the effect of reactor geometry on the impurity profile.Establishing this handshake between the physical asset and the process model early in the development has a lot of benefits for sustained cost efficiency of the future manufacturing process. For instance, it allows for optimization of yield and cycle times to the existing asset infrastructure. Furthermore, we can achieve quality reliability critical to our customers by establishing end-to-end correlation models that link the quality of incoming raw materials to finished good impurity profiles.Finally, we can achieve the lowest possible carbon footprint and minimize waste streams and energy intensity via process intensification by matching the unit operation sequence to the specific thermodynamics and kinetics of the process.SEMI: How can advanced packaging contribute to the pursuit of net zero? Vom Stein: Ultimately in a successful process design, we aim to achieve the maximum yield of value-added product with minimal input of resources and raw materials. So, there is an intrinsic synergy between highly intensified processes and their carbon footprint. The digitalization of process design allows us to track the CO 2 footprint during every iteration of the design. Establishing this tracking as a routine design KPI is one of the key initiatives to drive net zero semiconductor material solutions.In addition, advanced process design is a key enabler for circular value streams. We are currently working on multiple projects to recycle waste streams and re-feed them as raw materials in our processes. We are also exploring how our chemical process technology can aid our customers’ recycling efforts such as reusing lithography cleaning solvent waste streams.SEMI: In your previous talks, you emphasized the importance of diversity, equity and inclusion (DE I). How is this related to the digital revolution? Vom Stein: In the not-so-distant past, my team consisted mainly of process chemists and engineers. Now, we are working with data scientists, model developers, automation experts and many more substance matter experts on our projects. This work requires an inclusive culture to maximize the impact of these diverse sets of insights and disciplines.We also must acknowledge that, in many instances, we are exploring unchartered territory that requires a “leap of faith” culture trusting in digital models. Imagine, for example, a production plant director who is used to a stepwise physical scale-up, now being onboard with skipping physical scale-up steps by using predictive process models. It takes time to really establish a trust in the “power of data.” This type of culture is championed at Merck KGaA, Darmstadt, Germany on all levels: from CEO to the production operator. Our DE I Report showcases how we continuously build belonging for over 64,000 employees across the globe.SEMI: Merck KGaA, Darmstadt, Germany is a key contributor to semiconductor innovations. How important is it for Merck KGaA, Darmstadt, Germany to collaborate with other industry leaders to achieve goals in matters such as sustainability and DE I? Vom Stein: Collaboration with our customers and OEM partners is a key piece of achieving the molecular precision necessary to drive technology evolution that serves as the backbone to society. More and more, we need to link our material solution manufacturing process to the process parameters of the tools in the fab, ultimately improving the chip yield of our customers. To transition from the nanometer era to the angstrom era, we must establish these process correlations end to end along the value chain, which is why we are heavily engaged on our Athinia collaboration framework.Besides technology enablement, sustainability is the next avenue where cross value chain collaboration is a must to lower the CO 2 and energy footprint of our industry. To this end, we have started a joint program with Intel on AI-enabled sustainable semiconductor processes.The importance of industry collaboration is why I was so honored to participate at SEMICON Europa together with representatives from leading companies.SEMI: What did enjoy about SEMICON Europa 2023 that you would like to experience again in 2024? Vom Stein: I was really impressed by the SEMICON Europa 20 Under 30 recognition program launched during the show. The program honored the brightest young leaders who have demonstrated success in their careers in the microelectronics supply chain. We were very happy with the acknowledgement of one of our brightest minds at Merck KGaA, Darmstadt, Germany, Balazs Bordas, Digital Twin Implementation Lead. He has been instrumental for many of our pioneering efforts in this space.Such recognition programs are very important for our industry and can make a significant difference in the perception of the semiconductor industry and its ability to motivate and attract more talent. I personally hope to see similar programs in the years to come.Additional resources:Learn more about diversity and inclusion at Merck KGaA, Darmstadt, Germany.Learn more about Merck’s KGaA, Darmstadt, Germany modular lab automation approach.Merck KGaA, Darmstadt, Germany sponsored SEMICON Europa and SEMI Advanced Packaging Conference in 2023. Thorsten vom Stein is Director, Head of Process Design Semiconductor Materials at Merck KGaA, Darmstadt, Germany. Based in Darmstadt, Germany, he holds a PhD in Chemistry from the RWTH Aachen University and has extensive experience in Catalysis, Materials Science, Process Development and Value Chain Innovation.Serena Brischetto is Director of Marketing and Digital Engagement at SEMI Europe.

In an era where technology permeates every aspect of our lives, the semiconductor industry serves as the backbone of innovation. From IoT devices to data centers, every piece of technology relies on integrated circuits (ICs) such as intellectual property (IP) cores and system on chips (SoCs). As these technologies become increasingly pervasive, the importance of hardware security assurance in the design and development of IP and SoCs cannot be overstated. Evolving cyber threats and sophisticated attacks make it essential for vendors to integrate advanced security measures into their workflows.Market Pressures Driving Demand for Enhanced Hardware Security The semiconductor market is projected to reach $1 trillion by 2030. At the same time, semiconductor devices and system designs are becoming increasingly complex. With that complexity comes the added difficulty and effort required to conduct thorough security analyses. Additionally, competitive pressure to reduce time-to-market means that vulnerabilities can be more easily overlooked or exploited, making it crucial for the industry to adopt automated security solutions. As more products are deployed in critical systems, from consumer electronics to national infrastructure, the stakes become even higher, underscoring the necessity for robust security measures.According to the SEMI Electronic Design Market Data (EDMD) report, in 2023, the electronic design automation (EDA), semiconductor IP, and related services market reached $17.1 billion, fueled by the increasing complexity of semiconductor designs and the growing emphasis on security. While the overall EDA market is growing at a 7.4% compound annual growth rate (CAGR), the semiconductor IP segment is expanding at 9.7%, and in comparison, the logic verification tools market alone is surging ahead at 24.2%. Deeper verification processes and tools are needed to not only handle the rising complexity of semiconductor designs, but also to support the growing emphasis on secure-by-design principles to ensure robust and reliable products in an evolving technological, security, and threat landscape. As a result, the market for logic verification tools — a key component of the EDA market — is surging. The Rising Cost of Cyber Threats from Data Breaches and Architectural Flaws Pavani Jella, Silicon AssuranceThe average cost of a data breach is $4.88 million1, encompassing lost business, regulatory fines, legal fees, and damage to brand reputation. As the semiconductor market grows, the potential financial impact of security breaches due to hardware vulnerabilities also escalates. Companies must invest in robust security measures to mitigate these risks and protect their financial health.Cyber threats from the exploitation of architectural flaws are another threat. Plundervolt is one example of an architectural flaw that could lead to hardware exploitation. Discovered by ethical hackers, Plundervolt is the name of an attack that exploited voltage fault injection to compromise the security of Intel processors. By manipulating the voltage supplied to the CPU cores, attackers could induce errors in the SGX enclave, allowing them to leak sensitive data or even bypass security protections intended by the enclave. This flaw was particularly concerning because it operated at the hardware level, making traditional software security measures ineffective. The attack leveraged the SoCs’ power management features, specifically dynamic voltage and frequency scaling (DVFS), to achieve its malicious objectives.Exploiting such a vulnerability could lead to the exposure of sensitive data, such as cryptographic keys and proprietary information, compromising the confidentiality of secure enclaves. This breach could erode trust in an IP or SoC provider’s security features, particularly in environments that rely on using the IP or SoC for protecting critical data. In cloud environments, a successful exploit could result in multi-tenant data breaches, impacting numerous users.The vulnerability also poses risks to secure applications, potentially leading to manipulated outcomes and decrypted communications. Businesses could face significant financial losses, operational disruptions, and regulatory consequences due to such an attack. It is a stark reminder of how architectural flaws in SoCs can be exploited, leading to severe security breaches that are challenging to mitigate without hardware-level fixes.Industry Believes Hardware Security Assurance Is a Key Priority A majority of security professionals from a diverse group across industry, defense, government, and academia rate hardware Trojan detection, IP piracy protection, and SoC vulnerability assessment as high priorities. This prioritization reflects the industry's awareness of the critical importance of security measures in maintaining the integrity and reliability of semiconductor products.As a result of this awareness, investments in cybersecurity are expected to reach $345.4 billion by 2026, growing at a CAGR of 9.7%2. This substantial investment demonstrates the global commitment to enhancing security measures across all industries, including semiconductors, to combat the escalating threat landscape.New EDA Tools and Investments Needed to Combat Cyber Threats The adoption of new EDA solutions is essential, despite the initial costs. Costs can range from $100,000 to $1 million per license for general EDA design and verification tools, depending on the complexity and capabilities of the software. Pre-silicon security EDA tools can detect vulnerabilities early in the design phase, significantly reducing the risk of exploitation and the need for costly post-production fixes while enhancing product reliability. Secure-by-design principles ensure that security measures are integrated throughout the development process, rather than added as afterthoughts.Integrating these new tools also requires investment in training and potential adjustments to existing workflows. However, the improved security and efficiency provided by these tools can offset these initial costs.While the costs of acquiring advanced EDA tools and deploying them in the workflow is significant, the investment is justified by the long-term benefits of enhanced security and reduced risk of costly breaches. Secure-by-design practices can prevent significant financial losses from security breaches, offering substantial long-term savings. Companies that invest in robust security measures are better positioned to demonstrate market leadership and build customer trust and loyalty, while avoiding the reputational and financial damage associated with breaches.ConclusionThe semiconductor industry is at a critical juncture where the application of advanced EDA solutions for hardware security is not just beneficial, but essential. The time to act is now.The increasing sophistication of cyber threats and the financial repercussions of security breaches make it imperative for IP and SoC vendors to adopt advanced EDA security assurance solutions to secure their designs. By investing in cutting-edge EDA tools and prioritizing security from the earliest stages of design, vendors can safeguard their products, maintain market competitiveness, and protect against the ever-evolving landscape of cyber threats.References1. IBM Cost of a Data Breach Report 20242. KPMG 2024 Global Semiconductor Industry OutlookPavani Jella is the Vice President of Business Development at Silicon Assurance, a member of the Electronic System Design Alliance (ESDA) a SEMI Technology Community. Silicon Assurance specializes in hardware security assurance solutions. With a strong background in the semiconductor and EDA industries, Pavani plays a pivotal role in driving strategic growth and fostering innovative partnerships. Passionate about the intersection of technology and security, she helps organizations adopt state-of-the-art solutions that ensure the resilience and trustworthiness of their hardware systems.

Executive Advisor Jeff Lewis held the position of Vice President of Marketing and Business Development for Artisan Components, one of the early companies developing blocks of intellectual property. Lewis, who worked at Artisan from 1996-2000, and his colleagues were members of an elite group who built the mega-successful IP market, estimated today at $7.48 billion. Arm acquired Artisan Components in 2004 for $913 million.In my role as Executive Director of ESD Alliance and publisher of the quarterly Electronic Design Market Data (EDMD) report that includes IP, I recently talked with Lewis about what he remembers from the early days of IP.Smith: You were part of the IP revolution. What were the high points and low points that you most remember? Lewis: The high point was starting with a relatively blank slate and innovating. Some things worked, some didn't. We kept trying different things and seeing what would work with plenty of failed tries, successes, and repeats. We got a chance to be on the ground floor of a new industry. Another high point was watching this nascent industry emerge into a powerhouse. In the ‘90s, EDAC (Electronic Design Automation Consortium, the predecessor to the ESD Alliance) wasn't interested in tracking IP. As the IP market started growing, EDAC was all over it because it helped pump up the size of the electronic design automation (EDA) industry. Suddenly, IP had become a big enough industry that people were starting to care. And of course, there were successful public companies like Arm, Rambus, Artisan, and others licensing IP. It was fun being part of that.The low points were the hard part. While everything was new for us, it was also new for customers. They had intense resistance to licensing IP that many viewed as product development. They would want the IP company to develop something under a consulting or NRE contract, and then they would own the product and all the IP around it. They wanted to own everything. Many companies had that mentality in the early days and were resistant to licensing or paying royalties.As a side note, Gary Smith, former analyst for Dataquest, now Gartner Group, who died in 2015, and I had an ongoing debate. We went to lunch quite frequently and he would say, “IP is great, but you aren't IP. You are a standard cell, and it is not IP.” It was one of his standard statements.He would make various presentations, and I would argue: “You can't think of it as a cell, think of it as an entire library. It's an entire library with all the design views, layouts, test and qualification data, and everything else. That’s intellectual property. Plenty of intellectual property goes into developing it.”He eventually changed his mind and agreed when he saw the revenue and the value –– IP companies do it better and cheaper than in-house development.A final high point was getting the idea and value of IP across to customers. Smith: At what point did people start to believe IP was a real market and they could trust a vendor? Lewis: I don't know if there was an inflection point. More and more people started getting used to the idea that IP was an industry. Arm was probably the major catalyst. Artisan had two different engagement models. One was the integrated device manufacturer (IDM) model. Mark Templeton, co-founder and CEO of Artisan who died in 2016, and Lucio Lanza, Managing Partner of Lanza techVentures and Artisan’s Chairman, are credited with developing the royalty model and the intellectual property category. They drove it with the IDM model. Executive Advisor Jeff LewisCustomers knew they were paying for a license, understood the terms and became both the licenser and the user of this technology. It was different when Artisan went to the foundry model, which extended the IDM model to the rapidly growing foundry space. In this model, Artisan had the ability to widely disseminate its IP to all the foundry customers for free. However, calling it a “free library” is a misnomer, because often overlooked in this process is that the foundry paid up front for every one of those libraries, and it also paid a royalty on each design that used them. Artisan was profitable from day one by building a library or memory compiler. The engagement model was one where Artisan could proliferate these to the foundry’s users. They would get the library, and the royalty would come from the foundry. Users were beneficiaries – they had a simple license agreement, but unless they needed some customization, they weren't writing checks to Artisan.From the user’s perspective, it was great. They got free libraries and IP. That helped open people’s eyes to the model that could be a good thing. Artisan had 1,000 users at one point, and it helped drive the proliferation of IP use in the industry.Smith: Is that foundry model still in place? Lewis: Largely, yes, with some exceptions because foundries have a standard library that can be used. They have some specialized IP that customers license. While there are variations, foundries provide libraries to their customers. TSMC has engineers developing libraries for its own processes. For a long time, Artisan was the standard IP provider for most of the foundries. Smith: How did companies overcome verifying and testing IP? Were engineers skeptical about buying from an unknown/unproven company? Lewis: This is an important and critical question. Engineers were skeptical about buying from an unknown or unproven company. Artisan’s library quality was our biggest selling point, and it was the same with Arm and Rambus. Size and reputation were a huge advantage.The key was to have a major win that demonstrated your bona fides, and our biggest early win was our work on the Sony PlayStation. At that time, LSI Logic was developing the chips for the PlayStation, but was looking to outsource some of the critical blocks, such as the embedded SRAMs. Sony engineers were nervous and wanted to meet the IP companies to see what they were doing, because the fate of their chip was resting on these little companies. Artisan developed high-performance embedded SRAMs that replaced the existing LSI SRAMs. Our memories were about half the size of the LSI SRAMs, higher performance, and worked the first time.What’s instructive is how Artisan later got the foundry relationships going and sold libraries. Enabling first-time success is a quality argument, because the design would work the first time. At that time, almost every foundry library had bugs in them that caused silicon failures after tape-out. Our primary argument to engage foundries was our impeccable QA story. We had customer testimonials confirming that the foundries would not have library-related failures. When foundries scheduled a volume like a PlayStation ramp, they couldn’t afford a production “bubble” or “hole” in their production schedule from a library bug causing a chip not to work and requiring a re-spin.That's why the argument on quality and first-time success was critical to TSMC.One more thing on quality, and this ties specifically to Artisan and almost all IP companies. Any company that focuses on a mass proliferation model must ensure their product has no quality problems. Mass proliferation needs to be as low touch as possible, so engineers can use it without constantly calling for support. Quality is an absolute fundamental before mass distribution, because the fastest way to go bankrupt is to massively proliferate a faulty product. Smith: According to the EDMD report two years ago, IP surpassed front-end EDA tools as the highest category. Are we now shifting into a world where IP in the form of chiplets may become the dominant player? Lewis: I think the shift is coming. These are different incarnations of Moore's Law and the Carver Mead-structured VLSI. Sometimes the structure may be a chiplet, or the structure may be embedded.Is it virtual or is it actual? Engineers will make tradeoffs with pros and cons of embedding it or keeping it separate. The deciding factor is which silicon process is best and how it will be implemented. The SEMI EDMD report’s tracking of the Semiconductor Intellectual Property (SIP) and its rise to one of the market’s leading category. Smith: You worked for several IP companies that were offering process-related IP. That's a completely different type of market selling cycle, correct? Lewis: It is, because I focused on technology licenses for manufacturing processes, as opposed to the much more understood design IP that was developed for the existing manufacturing processes. Getting inserted into a company’s manufacturing process is much more difficult and challenging.If a company is licensing a technology that modifies the front-end process, then the process parameters will change, presumably for the better. The re-optimization can be like whack-a-mole. While some parameters get better, some may get worse, and further re-optimization can be required. This can go through several cycles until the process converges. This also means that all existing IP must be recharacterized and/or redesigned, which is why it is best to insert a new technology at the beginning of the node development rather than as a retrofit.Adding new process technologies is inherently difficult unless it’s a separable piece. For example, many new memories such as ReRAM or MRAM are licensed technology and separable, because they are set up separately in the metal stack. They don't touch the transistors.For a long time now, companies have been able to pick and choose whether to do in-house development or procure design IP from a third party. We're now starting to see the same thing in process development, because they are getting so complex, and no one can be an expert in all areas. I see process IP as paralleling the early days of design IP, but with a 30-year delay. Back then, most customers were reluctant to procure design IP because they felt: “We can do it all in-house.” Almost no one says that today, and I think this gradual acceptance will apply to process IP as well.Smith: Should Mark Templeton be considered the innovator and creator of the IP industry? Lewis: I’m not sure there’s anything I can say about him that hasn’t been said already. He was a great guy and an important thinker. I credit him for doing an excellent job crafting a successful company. And, of course, Lucio Lanza was absolutely instrumental as well. He pushed Artisan to do royalties, and Mark helped drive it to fruition.About Jeff LewisJeff Lewis is one of the pioneers of the semiconductor IP industry, participating since its inception in the mid-1990s. Lewis is currently Executive Advisor for senior management and investors for semiconductor and AI companies. He was previously an operating executive serving as Senior Vice President of Business Development and Marketing at Atomera Incorporated, Spin Transfer Technologies, SuVolta Inc., and Innovative Silicon Technologies, and held operating roles at Synopsys, VLSI Technology, and HP. Lewis earned an MBA from the UC Berkeley Haas School of Business, and has a bachelor’s degree in electrical engineering, and a bachelor’s degree in economics from UC Berkeley.Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Technology Community.

Use of machine learning and artificial intelligence (ML/AI) is on an exponential rise across fields1 including all aspects of the semiconductor industry. In the last decade, the use of ML/AI exploded in the areas of speech recognition, facial recognition, smart phone features, search engines and now large language models like ChatGPT, Bard AI, and CoPilot. The ML/AI growth has been enabled by massive data storage capacity and increased compute performance, leading to projections for the semiconductor industry to reach over $1 trillion in annual revenue by 2030, with about 50% of the industry’s growth related to GenAI2. Figure 1: McKinsey Company on GenAI driving semiconductor industry growthAs semiconductor manufacturing drives toward Industry 4.0, SEMI member companies have a vision of Industry 5.0, truly adaptive manufacturing, integrating human creativity with robotic precision enabled by AI. Along that path, automation and data exchange in every step of manufacturing is essential, with data acquisition, data integrity and relevance, and operational Digital Twins3 as defined steppingstones to the factory of the future.Based on growing member interest in ML/AI, in 2019, SEMI assembled technology communities that quickly engaged in AI discussions and proofs of concept, discovering gaps in the path to Industry 4.0. Successful demonstrations of the value of AI in chip manufacturing process development and factory efficiency, not to mention GenAI uses in society, hastened the pace to produce faster, more powerful chips to accommodate the computation and communication requirements. Recognizing the industry opportunity and the mounting role AI plays in the semiconductor supply chain, SEMI initiated several thought leadership efforts, namely the Smart Manufacturing Initiative, Smart Data-AI Initiative, and the Future of Computing think tank.Smart Manufacturing According to the SEMI World Fab Forecast, over 100 new and expanded wafer fabs will begin volume production by 2027. This massive capacity expansion will need to achieve the highest possible operational efficiency and performance. To this end, the Smart Manufacturing Initiative is a technology community with over 120 member companies collaborating pre-competitively to transform manufacturing. The SEMI Smart Manufacturing Global Executive Committee (GEC), outlined a roadmap vision for the cognitive factory of the future based-on technology, sustainability and future talent. The GEC has been working with members to realize that vision. Figure 2 describes this vision in terms of the technology progression needed and the approximate timeline for implementation by most manufacturers. The proliferation of this vision through Smart Manufacturing Forums at SEMICON events around the globe, newsletters and blogs has garnered enormous interest and participation in the initiative and is central to the mission of connecting and raising awareness within the ecosystem. Figure 2: AI-Driven Smart Factory (Point Systems to Autonomous Solutions) To move the needle on this vision, industry experts in the initiative successfully created and launched the Industry 4.0 Readiness Assessment Model (IRAM) to help assess technology deployment progress. IRAM adoption is steadily growing. Modern front-end and back-end lines produce an extraordinary amount of multi-modal data from a variety of sources, and this is key to success in unlocking the potential of AI in manufacturing environments. The initiative’s global working groups on Data Architectures and Smart Control Room among others are working towards a holistic Cognitive Factory framework uniting the vertical and horizontal flow of information. Integral to the Cognitive Factory are smart manufacturing standards, that will accelerate the vision outlined above, and without which local solutions are unlikely to scale.In 2023, the Smart Manufacturing Initiative brought together industry leaders in a unique Digital Twin workshop to align on the state of semiconductor development and usage. The key takeaways from this workshop are captured in a white paper that highlighted the need to accelerate efforts in multiple areas including standards. Along with SEMI International Standards, Smart Manufacturing supports other standards development organizations (SDOs) and NIST standards development, for example, to identify and drive critical standards for Cognitive Factory implementation. The initiative is planning future workshops on Cognitive Factory Framework requirements, Digital Twins, and Smart Data AI in the coming months. that highlighted the need to accelerate efforts in multiple areas including standards. Along with SEMI International Standards, Smart Manufacturing supports other standards development organizations (SDOs) and NIST standards development, for example, to identify and drive critical standards for Cognitive Factory implementation. The initiative is planning future workshops on Cognitive Factory Framework requirements, Digital Twins, and Smart Data AI in the coming months.The GEC has identified critical interrelationships in addition to the technology focus. At the intersection with sustainability, the initiative has formed a collaborative task force with the SEMI Semiconductor Climate Consortium (SCC) to develop a bottom-up technology roadmap that can be used as a blueprint for device makers to meet their proclaimed sustainability goals faster. The task force organized a technical session at SEMICON West 2024 and will be releasing a white paper in the near future. Similarly, the initiative is working with the SEMI Foundation to identify necessary future skills and to make training available through SEMI University. Smart Data AI – Applying AI to Semiconductor OperationsSEMI’s Smart Data-AI Initiative started by assembling a group of interested companies to explore the pivotal role AI could play in the industry and to address the criticality of data. All stakeholders agreed that a formidable challenge was (and still is) the integrity of that data and the security of sharing that data, which is considered IP to most. The optimal implementation of ML/AI techniques can only be gained by access to the comprehensive data set which is owned by numerous supply chain partners. Consequently, semiconductor R D, process and design have not yet realized the full benefit of Data-AI advances. In response, the initiative developed a framework to create value for members and support industry progress. Four pillars underpinning the strategy are:Educating stakeholdersBuilding communitiesExecuting proof-of-concept projectsDeveloping industry standardsTo explore the data challenges the subject matter experts highlighted, a collaborative proof-of-concept (POC) project was proposed in 2019 and accepted by the initiative's partners at Army Research Laboratories4 along with academic and industry partners. The project has completed two phases and is starting on its third phase under the expert guidance of an Industry Advisory Council (IAC) comprised of leaders in the Smart Data-AI community.The POC project, being conducted by principal investigators at Cornell University, demonstrated significant accomplishments from the first two phases, including:An AI model to predict device geometry by optimizing photolithography and plasma etching processesInitial demonstration of secure data-sharing techniques with software-hardware co-optimizationInnovative metrology ideas to train AI algorithms rapidlyStudents trained in cross-disciplinary skills to address the industry’s critical talent shortageFurthermore, the visionary objectives laid out at the initial stages of the POC proved to be synergistic with the strategic goals of the CHIPS Act5, which articulates the need for “collecting, aggregating, and sharing data sets that enable benchmarking and operational improvements, tools development, the creation of digital twins, and training AI models,” and that “the NSTC could develop a methodology for the voluntary sharing of data that protects the proprietary component and national security while enabling access to appropriate performance data.” Phase 3, to be completed by August 2025, will advance the state-of-the-art toward the following specific objectives:A framework to create and integrate Digital Twins of semiconductor R D and manufacturing process toolsAbility to explore processes and generate virtual devices swiftlyDefined interfaces to combine models for each process module or toolAccurate AI-based models for executing virtual process flows to build virtual devicesAdvanced solutions for secure data-sharing across the ecosystem – for example, federated learning where raw data is protected for each entity by building models locally, and only the outputs of the local models are used to build flow-level AI modelsFoundation for future industry standards for secure data-sharing and for interfaces in the virtual innovation environmentSEMI continues to build the collaborative community for Data-AI and strives to synergize with broader efforts such as the Digital Twin Manufacturing Institute, NSTC, and NAPMP in the U.S., and international standards development. Smart Data AI – System-level Innovation for AI – Future of ComputingThe cross-collaborative and synergistic objectives of Smart Manufacturing, the Smart Data-AI proof-of-concept work, and SEMI Standards merge to advance the state-of-the-art. The objective is to help members realize the full value of technology and innovation. In addition to improving semiconductor operations using AI, the efforts also strive to enable SEMI members to participate in, and ultimately profit from, market growth opportunities. Continued progress in AI is crucial both for the industry’s march towards $1 trillion in annual revenue, and for continuing to realize AI’s benefits to society.There are some hurdles to overcome in such a dynamic market. AI models, and the data they process, are outpacing hardware advances, posing a major roadblock for continued progress. As GenAI becomes more pervasive, the performance and power challenges continue to multiply, and require significant innovation in both hardware and software. While individual companies will develop competitive products in this domain, the entire ecosystem needs to evolve in a synergistic manner. As a global industry association, SEMI can play an important role in ensuring this. SEMI started a series of workshops and technology sessions to develop the community and identify opportunities and challenges. The first in this series was a joint workshop with McKinsey Co., held in October 2023, with a focus on innovations in “Domain-Specific Architectures.” Strategically, it brought together thought leaders from three diverse communities - start-ups, investors, and SEMI member companies across the supply chain. This was followed by an overcapacity audience at the Future of Computing session at SEMICON West 2024, where we explored AI-specific hardware with leaders in academia and industry. The Initiative’s next planned event in October 2024 is a focused workshop that is designed to be highly interactive and bring together visionaries and thought leaders from across the value chain – materials, devices, architectures, algorithms, and critical enabling technologies such as photonics, chiplets, advanced packaging, and 3D and heterogeneous integration. The overarching goal is to identify pre-competitive collaborative actions that would help the entire industry. The “Future of Computing” is the broad path to the industry’s future success. While AI systems are the current major wave on this path, future waves may be about heterogeneous integration of photonics and other components, and ultimately, quantum technologies joining the mainstream. SEMI continues to monitor these future trends, strengthen the ecosystem and enable innovation through pre-competitive collaboration, and accelerate implementation through standards.SEMI is fostering today’s collaborations while helping the industry navigate the future of electronics.Melissa Grupen-Shemansky is CTO at SEMI, Pushkar Apte is a Strategic Technology Advisor and Leader of the SEMI Smart Data-AI Initiative, and Mark da Silva is Senior Director of the SEMI Smart Manufacturing Initiative.Definitions and References:1https://arxiv.org/abs/2405.15828 Eamon Duede, William Dolan, Andre Bauer, Ian Foster, Karim Lakhani2McKinsey Company3Digital Twins for semiconductor manufacturing operations are dynamic, predictive, data-driven virtual models of a physical asset, process, or an entire factory, constantly synchronized with its real-world counterpart through real-time data streams and analytics4Research was sponsored by the Army Research Laboratory and was accomplished under Cooperative Agreement Number W911NF-19-2-0345. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the Army Research Laboratory or the U.S. Government. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation herein.5“A Vision and Strategy for The National Semiconductor Technology Center (NSTC)” published by the CHIPS R D Office.

Presentations at this year’s FLEX Conference illustrated the ongoing development of manufacturing tools and processes, materials, and test and reliability evaluation techniques for the growing field of hybrid electronics, which includes printed electronics and flexible hybrid electronics (FHE). Additionally, the field includes the use of additive manufacturing processes for electronics packaging and system assembly, from die attach to flexible printed circuits.Hosted by FlexTech, a SEMI Strategic Technology Community, the conference provides an opportunity for the device making supply chain to connect to R D, design and manufacturing innovations. A review of some of the key developments highlighted in FLEX presentations follows.Innovations in Flexible Printed CircuitsTokyo-based Elephantech has been focused on using advanced inkjet systems to produce flexible printed circuits. Using additive methods instead of subtractive to produce PCBs can enable reductions in carbon footprint, copper usage and water consumption. In order to achieve these benefits, Elephantech has developed processes for combining inkjet printing of metals and electroless plating. The company synthesizes copper nano particles, which it uses to formulate metal ink. It has implemented artificial intelligence to increase print accuracy, showing the capability of average drop position error of less than 2μm, and depositing 20μm droplets into 40μm grooves and wells (Fig 1).Fig. 1. Elephantech inkjet results showing ~2μm precision and prototypes with 50μm line widthExamples of Elephantech’s use of flexible printed circuit technology include a set of switches for a curved monitor and a pressure sensor with reduced footprint and component count. The company intends to directly compete with larger, rigid PCBs, and is developing a mass-production system with 57,840 nozzles that can process sheet sizes of 500 x 830 mm.Traditional processes for component attach on PCBs include mass reflow ovens, thermal compression bonding, and spot laser reflow. Laserssel has developed laser selective reflow, which promises warpage- and damage-free bonding at increased processing speeds. In addition to improving the productivity of rigid PCB production, the laser selective reflow could also enable in-line processing of roll-to-roll flexible printed circuits, replacing the use of trays for bonding to flexible printed circuits.Scrona, which spun out from ETH Zurich, has developed MEMS-based printheads to improve electrohydrodynamic (EHD) printing. By using an electric field to pull droplets out of the print nozzle, EHD can enable much higher print resolution (sub-micron, compared to tens of microns), and enable the use of higher viscosity inks than would be possible with traditional inkjet heads. While EHD has been under development for some time, its application has been limited by crosstalk, in which the electric fields of adjacent nozzles interact with each other, and the requirement for the nozzle to be within tens of microns from the substrate to enable high print accuracy.Scrona’s MEMS-based nozzles address these EHD problems by shielding adjacent nozzles to prevent crosstalk and by creating a uniform electric acceleration field, which increases print distance to the order of a millimeter. The company has used its system to print a variety of inks on different substrates, as well as conformal printing on 3D surfaces (Fig. 2).Fig. 2. Example of printing silver wires across a polished glass edge; line pitch 25μm, glass thickness 1mmThe Rochester Institute of Technology (RIT) has been developing an additive technique called liquid metal droplet jetting, which can deposit metal traces functionally equivalent to solid wires. The process uses metal wire as a feedstock, which is a fraction of the cost of nanoparticle metals. While tin, zinc, and aluminum have been used, silver and copper are still under development. The wire is melted in a micro-crucible, which feeds a nozzle; metal droplets are then jetted on demand in an argon environment to prevent oxidation (Fig. 3, l). Upon hitting the substrate, the drops solidify into metal traces equivalent to solid wire, quickly enough to avoid melting flexible films, and without curing or drying.Several methods have been explored to eject the jets from the nozzle, including magnetohydrodynamic using electromagnetic pulses, piezo-actuated pistons, and pneumatic jetting using compressed gas (Fig. 3, r). These techniques range from high-jetting-frequency and high-cost to simple and low-cost but low-frequency. Higher frequency enables overlap of droplets, increasing conductivity, and reduced processing time.Fig. 3. Concept of liquid metal droplet jetting (l); pneumatic droplet ejection approach (r)In addition to ongoing development of deposition tools and processes, the material set for additively printed electronics continues to expand. Iris Light Technologies, which spun out of Argonne National Lab and Northwestern University, is developing photonic inks for wafer-scale production of active devices including photodetectors, LEDs, and lasers. The semiconductor-based ink can be deposited via aerosol jet onto silicon wafers. Iris Light is focused on 2D semiconductors, specifically black phosphorous, which has a wider spectral coverage than graphene, is tunable in emission and absorption, and has high mobility.An example of the broadening of the additive manufacturing supply chain, Kraetonics has developed software for creating slices to be used in designing 3D-printed structures and elements. The software enables manufacturing 3D volumetric circuits with reduced size, weight, and power compared to 2D PCBs. The process involves 3D printing of hybrid mechanical-electrical assemblies such as circuits and antennas.Innovations in Test and ReliabilityAn area of active interest in the hybrid electronics community is that of test and reliability. American Semiconductor, a developer of flexible circuitry, and Bayflex, a value-added partner of Japanese equipment company Yuasa, are conducting a project on dynamic harsh environmental FHE reliability testing. The goal is to identify root causes of FHE material and system failures.The companies are developing extended temperature and humidity tests to determine FHE system lifetimes and identify causes of failures from physically deforming FHE materials and systems in harsh temperature and humidity environments. Materials under consideration for testing include:Copper on polyimide substrate with a small outline package IC and surface-mounted componentsNobleflexTM, a multilayer substrate with gold on polyimide in development for medical devicesSilver on PET substrate, with small outline package IC.The team is soliciting other test devices and is planning to coordinate with ongoing development of FHE test standards coordinated by SEMI.Henkel reported on an investigation of accelerated temperature cycling test methods, in which the company applied different combinations of temperature range, stress, and frequency of mechanical force in an effort to reduce cycle time for testing component attach reliability. The study was able to achieve similar failure modes using an accelerated test method in the case of a bonding position shift in which cracking of the die attach film was the failure mode (Fig. 4, approach 4). The study found the greatest acceleration in the case of reduced thermal shock cycles (Fig. 4, approach 1).Fig. 4. Approaches evaluated for accelerated testing of component attach.Engineering consulting firm Exponent presented the results of a study on mechanical testing for characterizing fatigue performance of flexible electronics, conducted with continuous monitoring of fatigue for 6-pin flexible flat cables from seven different vendors. Exponent found that continuous monitoring during bending fatigue testing provided greater resolution in test results including detection of intermittent failure in each sample. The study also found that strain amplitude was a critical factor for determining fatigue life, and that flat flexible cables with larger pitches showed improved fatigue performance.About SEMI FlexTechFlexTech, a SEMI Strategic Technology Community, promotes the growth, profitability and success of the flexible hybrid electronics industry by developing educational forums, directing research, and promoting technology innovation.SEMI FlexTech members benefit from speaking and business networking opportunities, introductions to key industry players, research reports, technical funding, access to end users and industry advocacy at FLEX Conferences.Gity Samadi is Director of SEMI research and development funding programs and SEMI FlexTech and SEMI Nano-Bio Materials Consortium (NBMC). Paul Semenza is an advisor to SEMI on special projects. He was previously with NextFlex, the Flexible Hybrid Electronics Manufacturing Innovation Institute.