Technology and Trends

Automakers are currently evaluating prototypes of Viper from AdaSky, a Far Infrared (FIR) thermal camera that embeds custom silicon co-designed with and manufactured by ST in 28nm FD-SOI. The complete sensing solution aims to enable autonomous vehicles to see and understand the roads and their surroundings in any condition. “With the help of ST, we have created the first high-resolution thermal camera for autonomous vehicles with minimal size, weight, and power consumption--and no moving parts. ST’s access to, and expertise in, ultra-low-power design, IP that is fully qualified for automotive applications, and 28nm FD-SOI technology have been vital to meeting the severe power constraints that would challenge our sensors’ performance,” said Amotz Kats, Vice President Hardware, AdaSky. “We’re in a position to deliver a breakthrough solution to revolutionize and disrupt the autonomous vehicle market because of ST’s mastery of automotive qualification and its strong manufacturing supply chain, which grants reliability, long-term support, and business continuity to car makers throughout the whole life of their production.” Passive infrared vision, like that in AdaSky’s Viper, when used in a fusion solution, can help close the gaps to provide accurate sight and perception without fail in dynamic lighting conditions, in direct sunlight, in the face of oncoming headlights, and in harsh weather. The new camera uses an FIR micro-bolometer sensor to detect the temperature of an object. In an ADAS solution, Viper uses proprietary algorithms based on Convolutional Neural Networks to classify obstacles and show them in a cockpit display to give the driver an early warning. This warning comes several seconds earlier than it would when using a conventional sensor in the visible wavelength and is even faster than what is possible with the human eye. The two companies say that the Far-Infrared thermal camera extends ADAS sensor fusion capability with a new layer of information, helping pave the way to fully-autonomous driving in any condition. Prototypes are now under evaluation by carmakers with initial production targeted for 2020. (Read the full press release here.)

GlobalFoundries' new ecosystem partner program, called RFwave™, aims to simplify RF design and help customers reduce time-to-market for a new era of wireless devices and networks (read the full press release here). The program aims to give designers a low-risk, cost-effective path to highly optimized solutions that leverage GF's platforms including RF on FD-SOI and RF-SOI. The target is wireless applications such as IoT across various wireless connectivity and cellular standards, standalone or transceiver integrated 5G front end modules, mmWave backhaul, automotive radar, small cell and fixed wireless and satellite broadband. As such, the RFwave™ partner program provides GF customers with IP design elements, EDA tools, design consultation and services and OSAT product packaging and test solutions. These products and services are validated, and comprise a plug-and-play catalog of design solutions. With this level of integration, GF customers can create high-performance designs while minimizing development costs. Bami Bastani, senior vice president of GF’S RF Business Unit, says, “As a leader in RF, GF’s RFwave program takes industry collaboration to a new level, enabling our customers to build differentiated, highly integrated RF-tailored solutions that are designed to accelerate the next wave of technology.” Initial members of the RFwave Partner Program are: asicNorth, Cadence, CoreHW, CWS, Keysight Technologies, Spectral Design, and WEASIC.

Worried that you’re underhydrated after a heart-pounding run or bike ride? SEMI’s Nano-Bio Manufacturing Consortium (NBMC) has you covered – with a patch. A few years after the group undertook the sweaty task of creating a non-invasive health monitor, the patch that tracks electrolyte levels recently ended up stuck to the skin of U.S. Air Force volunteers.“During extra workout sessions at the Air Force Research Laboratory in Ohio, the volunteers wore on their backs adhesive patches that collected their perspiration," according to GE Reports. "Sensors in the patches were able to detect the specific levels of electrolytes in the sweat the volunteers released. That data was transmitted wirelessly to a laptop computer app where researchers could analyze it in real time.” Read more about the project in the GE Reports blog.The project came together when NBMC, a diverse group of companies, universities and organizations, brought their enthusiasm and interdisciplinary know-how across nanotechnology, biotechnology, advanced (additive) manufacturing, and flexible electronics to tackle the challenge of underhydration and dehydration. The idea was to develop a device that delivers reliable, wireless, actionable human performance data in a non-invasive way.Congratulations to GE Global Research, and the partners from the Air Force Research Laboratory, University of Connecticut, University of Massachusetts-Amherst, American Semiconductor Inc., University of Arizona, UES, Dublin City University and NBMC on these impressive strides in the field of health monitoring!Watch this video to see the patch in action! (https://www.facebook.com/GE/videos/1667584156643205/)Visit www.nbmc.org for more information.

Sales revenues for fluid management subsystems grew 28 percent in 2017 to $1.28 billion, breaking the $1 billion mark for the first time. Fluid management subsystems have now seen five years of consecutive growth, and 2018 is expected to extend the growth streak to six years for the segment.Fluid management subsystems control the delivery of process gases and chemicals onto the wafer during processing and may be located either on-tool or near the tool. This segment can be further divided into two main categories – gas delivery and liquid delivery subsystems. Gas delivery subsystems, such as mass flow controllers (MFCs), deliver gases or speciality chemicals to a vacuum process chamber, and liquid delivery subsystems typically deliver liquid chemicals to a wet processing module. Demand for gas and liquid delivery subsystems is roughly 54 percent and 46 percent respectively – a ratio that has not changed significantly over the past few years.Although fluid management subsystems account for approximately 10 percent of expenditures on all critical subsystems used on semiconductor manufacturing equipment, growth of other critical subsystems such as vacuum processing subsystems has been sluggish.Mass flow controllers (MFCs), however, are showing strong growth potential and are set to buck their historical slow growth trend as the industry transitions into sub 10 nm processing. At the leading edge, processes are becoming more vacuum intensive and the importance (and difficulty) of accurately controlling chemical delivery for deposition onto the wafer is increasing. Process operating windows are getting tighter and the specification ranges demanded by chipmakers are shrinking, posing challenges for existing MFC technology. The upshot is that new MFC solutions and technologies are needed to enable transitions to smaller nodes, providing an opportunity for growth in this segment.The fluid management subsystems market is currently dominated by Japanese- and U.S.-based vendors. Horiba is the largest player, accounting for 30 percent of total fluid management sales, and the rest of the market is extremely fragmented, with a raft of companies competing in this space.Given the large size and fragmentation of this segment, interest in these products in the coming year is sure to intensify as the race to find lucrative solutions to enable sub 10 nm processing heats up.For more information about VLSI Research and Critical Subsystems, visit www.vlsiresearch.com.

Following the immense success of last year's FD-SOI training day in Silicon Valley, the SOI Consortium has another one planned for the end of April this year. If you want to start learning how to leverage FD-SOI in your chip designs, this is a great place to start. Click here for information on how to sign up. ST Fellow Dr. Andreia Cathelin has put together another great line-up. World renowned professors and experts from industry will deliver a series of four training sections of 1.5 hours each, focused on energy efficient and low-power, low-voltage design techniques for analog, RF, high-speed, mmW and mixed-signal design. You'll learn about design techniques that take full advantage of the unique features of FD-SOI, including body biasing capabilities that further enhance the excellent analog/RF performances of these devices. Each section of this training day will take you through concrete design examples that illustrate new implementation techniques enabled by FD-SOI technologies at the 28nm and 22nm nodes – and beyond. The design examples will cover basic building blocks through SoC implementations. A global Q A session will close the day. Here's a little more info on how the day will unfold. Click on the slides to see them in full screen. Morning sessionsFDSOI-specific design techniques for analog, RF and mmW applications - Andreia Cathelin, Fellow, STMicroelectronics [caption id="attachment_11714" align="alignleft" width="300"] Quick preview from Andreia Cathelin's FD-SOI training session (Courtesy: STMicroelectronics, SOI Consortium)[/caption] Andreia Cathelin is ST's key design scientist for all advanced CMOS technologies, and is arguably the world's leading expert on leveraging FD-SOI in high-performance, low-power RF/AMS SoCs. Her course will first present a very short overview of the major analog and RF technology features of 28nm FDSOI technology. Then the focus moves to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits. She'll give design examples such as analog low-pass filters, inverter-based analog amplifiers and 30GHz and 60GHz Power Amplifiers, as well as mmW oscillators. There will be particular focus on the advantages of body biasing and special design techniques offering state-of-the-art performance. Circuit Design Techniques in 22nm FD-SOI for 5G 28GHz Applications - Frank Zhang, Principal Member of Technical Staff, GlobalFoundries [caption id="attachment_11716" align="alignright" width="300"] Quick preview from Frank Zhang's FD-SOI training session (Courtesy: GlobalFoundries, SOI Consortium)[/caption] Frank Zhang has designed chips using GF's 22nm FD-SOI (22FDX) process for WLAN, 5G cellular and automotive radar applications. His course will focus on how to take advantages of FD-SOI’s high-frequency performance at relatively low-current density to design high performance RF/mmWave circuits. Examples circuits include a 28GHz LNA, a 28GHz PA and an RF switch for 5G applications. The FD-SOI advantages such as low capacitance, high breakdown voltage and high-output impedance will be exploited in these design examples. This course will also discuss how to extend these techniques to applications at higher frequencies and/or higher current densities that are subject to extreme temperatures and EM requirements. Afternoon sessionsEnergy-Efficient Design in FDSOI - Bora Nikolic, Professor, UC Berkeley [caption id="attachment_11715" align="alignleft" width="300"] Quick preview from Bora Nikolić's FD-SOI training session (Courtesy: UC Berkeley, SOI Consortium)[/caption] Borivoje (“Bora”) Nikolić is known as one of the world’s top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI.) If you missed it, his team's RISC-V chip was cited as one of Dr. Cathelin's “Outstanding 28nm FD-SOI Chips Taped Out Through CMP” – read more about that here. His talk at the training day will present options for energy-efficient mixed-signal and digital design in FD-SOI technologies. He'll explain how to generate body bias and use it to improve efficiency, with examples in RF and baseband building blocks, temperature sensors, data converters and voltage regulators. The techniques will be presented in the context of UC Berkeley's latest RISC-V-based SoC, designed to operate in a very wide voltage range using 28nm FD-SOI. mm-Wave and Fiber-Optics Design in FD-SOI CMOS Technologies - Sorin Voinigescu, Professor, University of Toronto [caption id="attachment_11713" align="alignright" width="300"] Quick preview from Sorin Voinigescu's FD-SOI training session (Courtesy: U. Toronto, SOI Consortium)[/caption] Sorin Voinigescu is a world renowned expert on millimeter-wave and 100+Gb/s ICs and atomic-scale semiconductor device technologies. His lecture will cover the main features of FD-SOI CMOS technology and how to efficiently use its unique features and suitable circuit topologies for mm-wave and broadband SoCs. He'll begin with an overview of the impact of the back-gate bias and temperature on the measured I-V, transconductance, fT, and fMAX characteristics. Then he'll compare the maximum available gain, MAG, of FDSOI MOSFETs with those of planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz. Next, he'll provide biasing, sizing and step-by-step design examples for VCO, doubler, switches, PA, large swing optical modulator drivers and quasi-CML circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of 20nm and 12nm FD-SOI CMOS technologies. Sign Up Now!With over 100 attendees filling every chair in the auditorium, last year's training day was sold out. Although it was in Silicon Valley, people actually flew in from all over the world to be there. During the Q A at the end, most everyone prefaced their questions by saying, “Thank you. I really learned a lot today.” 2018 will be no different – except that it's sure to sell out even faster. Please note, though, that this is not a free event, so only the attendees will get copies of the slide decks. Here's key info you need to sign up. See you there!What: SOI Consortium's FD-SOI Training DayWhen: 27 April 2018, 7:30am – 5pm.Where: Crowne Plaza San Jose, Milpitas CA (parking is free)Registration fee: US $485.00 (includes training book, breakfast, box lunch and refreshments during breaks)How to sign up: Click here to go directly to the registration site.

Artificial intelligence (AI) is making headlines everywhere, offering a range of capabilities, including location and motion awareness — determining whether a user is sitting, walking, running or sleeping. Behind the scenes, AI is capturing volumes of data. Makers of smartphones and fitness and sports trackers, along with application developers, are all clamoring for this data because it helps them analyze real-world user behavior in depth. Manufacturers gain a competitive edge by tapping this intelligence: Using it to improve user engagement, they increase the perceived value of their devices, potentially reducing customer churn. How can consumer-product manufacturers tap the built-in capabilities of MEMS inertial sensors — which are already ubiquitous in end-user devices — to make the most of AI? Machine learningProduct manufacturers can easily build an activity classification engine using commonly available smart sensors and open-source software. Activity trackers, for example, use raw data first collected via the MEMS inertial sensors that are already installed in smartphones, wearables and other consumer products.With the building blocks in place, consumer-product manufacturers can apply machine learning techniques to classify and analyze this data. There are several possible approaches, ranging from logistic regression to deep learning neural networks.One well-documented method used for classifying sequences in AI is Support Vector Machines (SVM). Physical activities, whether walking or playing sports, consist of specific sequential repetitive movements that MEMS sensors gather as data. MEMS sensors make good use of this collected data, which can be easily processed into well-structured models that are classifiable with SVMs.Consumer-product manufacturers have gravitated toward the SVM model since it is easy to use, scale and predict. Using an SVM to set up multiple simultaneous experiments for optimizing classification over diverse, complex real-life datasets is far simpler than with other approaches. An SVM also introduces a wide range of size and performance optimization opportunities for the underlying classifier.Cost impacts of processing, storage and transmissionIn practice, recognizing user activity hinges on accurate live classification of AI data. Therefore, the key to optimizing product cost is to balance transmission, storage and processing costs without compromising classification accuracy.This is not as simple as it sounds. Storing and processing AI data in the cloud would leave users with a substantial data bill. A WiFi, Bluetooth or 4G module would drive up device costs and require uninterrupted internet access, which is not always possible.Relegating all AI processing to the main processor would consume significant CPU resources, reducing available processing power. Likewise, storing all AI data on the device would push up storage costs.Resolving the issuesTo resolve these technology conflicts, we need to do four things to marry the capabilities of AI with MEMS sensors.First, decouple feature processing from the execution of the classification engine to a more powerful external processor. This minimizes the size of the feature processor size while eliminating the need for continuous live data transmission.Next, reduce storage and processing demands by deploying only the features required for accurate activity recognition. In one example created by UC Irvine Machine Learning Repository (UCI), when an AI model was trained using a dataset of activities with 561 features, it identified user activity with an accuracy of 91.84 percent. However, using just the 19 most determinative features, the model still achieved an impressive accuracy of 85.38 percent. Notably, pre-processing alone could not identify these determinative features. Only sensor fusion enabled the data reliability required for accurate classification. Third, install low-power MEMS sensors that can incorporate data from multiple sensors (sensor fusion) and enable pre-processing for always-on execution. A low-power or application-specific MEMS sensor hub can slash the number of CPU cycles that the classification engine needs. The onboard software can then directly generate fused sensor outputs at various sensor data rates to support efficient feature processing.Finally, retrain the model with system-supported data that can accurately identify the user’s activities.Additionally, cutting the data capture rate can reduce the computational and transmission resource requirements to a bare minimum. Typically, a 50 Hz sample rate is adequate for everyday human activities. This may soar, however, to 200 Hz for fast-moving sports. Reducing dynamic data rate selection and processing in this way lowers manufacturing costs while making the product lighter and/or more powerful for the consumer.High efficiency in processing AI data is key to fulfilling its potential, driving down costs and delivering the most value to consumers. MEMS sensors, in combination with sensor fusion and software partitioning, are critical to driving this efficiency. Operating at very low power, MEMS sensors simplify application development while accurately analyzing motion sensor data.Combining AI and MEMS sensors into a symbiotic system promises a new world of undreamt-of opportunities for designers and end users.This blog post is based on an original article that first ran in EDN. It appears here with the permission of the publisher.

Large semiconductor fabs can devour electricity at clip of 100 megawatts per hour -- enough to power 50,000 homes1 and, according to a McKinsey study, more than automobile plants and oil refineries consume. So ravenous is their electricity consumption that some fabs have resorted to building their own captive power plants. Oversize fabs, depending on their location and local rates, can run up utility bills as high as $25 million each year, with electricity accounting for up to 30 percent of operating costs.Fabs use electricity to power HVAC, run cooling water, and for basic infrastructure. But the vast majority of electricity is gobbled up by semiconductor manufacturing process tools and their sub-fab support equipment such as vacuum pumps and abatement systems. In a typical fab, as much as 44 percent of the electricity is consumed by the processing equipment2. It’s not so hard to imagine. Etch and deposition tools need power to strike and sustain plasma, with multiple 1,000+ Watt RF power supply feeds per chamber and four, six or more chambers per tool, and vacuum pumps spinning and abatement running. The power load adds up quickly. Watts and WattsThe good news is that process tools aren’t processing wafers all the time. The bad news is that, in the past, there was no good way for the fab to know when process tools and support equipment weren’t running processes. Turning equipment off, or reducing power when not processing, wasn’t coordinated and standby states weren’t defined for readiness for a seamless power-up and return to processing. So what to do? Take action. That just what industry volunteers did when they met within SEMI’s Standards program and defined an equipment “idle mode” (SEMI E167 and SEMI S233). More recently, a SEMI Standard (SEMI E1754) was developed to define energy saving modes – how process tools communicate with sub-fab equipment, to reduce utility consumption when wafers are not being processed by the tool. Importantly, it also provides guidance on the standby state to return to full performance when the tool is needed to process wafers.5Good to be IdleThe semiconductor industry is now increasingly adopting a “smart idle” approach using these SEMI Standards. Fabs implementing these standards to take advantage of process tool idle periods can save more than 4.3 million € annually, according to AIS Automation modeling.6 This study also points to a savings of more than 16,000 tons of CO2 per year, the equivalent of taking more than 10,000 cars off the road.Who knew that recognizing when to be idle could bring such big rewards? If only I could apply that to my own life, but, for now, I will have to leave it to the fabs. SEMI International Standards volunteers make a huge difference to our industry every day. If you want to join the over 5,000 SEMI Standards volunteers (or join SEMI’s Sustainable Manufacturing eForum), with representation from over 2,000 companies, it’s free! Don’t be idle for this one, click here to join! http://semi.huihuidehui.workers.dev/en/standards/P041367 1Bringing Energy Efficiency to the Fab, McKinsey 20132http://semiengineering.com/saving-energy-in-the-fab/3SEMI E167-1213 - Specification for Equipment Energy Saving Mode Communications (EESM)http://ams.semi.org/ebusiness/standards/SEMIStandardDetail.aspx?ProductID=211 DownloadID=32573SEMI S23-0813 - Guide for Conservation of Energy, Utilities and Materials Used by Semiconductor Manufacturing Equipmenthttp://ams.semi.org/ebusiness/standards/SEMIStandardDetail.aspx?ProductID=211 DownloadID=31094SEMI E175-1116 - Specification for Subsystem Energy Saving Mode Communication (SESMC)http://ams.semi.org/ebusiness/standards/SEMIStandardDetail.aspx?ProductID=211 DownloadID=38765http://electroiq.com/blog/2017/06/how-semi-standard-e175-is-saving-energ...6SEMI Standards a Potential Help for Saving Energy, Bert Mueller, AIS Automation 2016

RF-SOI innovators Jean-Pierre Raskin of UCL and Bernard Aspar of Soitec changed the course for key RF chips. The industry has long recognized their contributions: their solution for “trap-rich” RF-SOI wafers is now the starting point to virtually every FEM in every smart phone on the planet (really!). And of course here at ASN we've been following their work for over a decade. Now more accolades are coming in. The latest is the 2017 European SEMI Award, which was given at ISS Europe 2018 for “...their seminal work with radio frequency silicon-on-insulator (RF-SOI) substrates” (read the press release here). As SEMI notes, the “...award winners’ pioneering research and collaboration with academia and industry led to major advances in RF switches and ushered RF-SOI technology from concept to worldwide adoption.” Aspar and Raskin were nominated and selected by their peers within the international semiconductor community. [caption id="attachment_11677" align="alignleft" width="150"] Bernard Aspar, Executive Vice President, Communication Power BU at Soitec Aspar founded CEA-Leti spinoff Tracit Technologies in 2003. He was appointed senior vice president of the Tracit Division (now the Communication Power business unit) when Soitec acquired Tracit in 2006. He has more than 15 years of experience in direct wafer-bonding and layer transfer. Aspar has filed more than 35 patents and co-authored some 100 scientific articles. He holds engineering and Ph.D. degrees in materials sciences and a master’s degree in microelectronics from the University of Montpellier, France.[/caption] [caption id="attachment_11678" align="alignleft" width="150"] Jean-Pierre Raskin, professor, Université catholique de Louvain (UCL) Raskin contributed to pioneering scientific studies demonstrating that silicon-based MOS technology could enable affordable, high-quality mobile devices. His findings led to the advent of RF-SOI technology and today impact the global microelectronics industry. He is an IEEE Senior Member, EuMA Associate Member and Member of the Research Center in Micro and Nanoscopic Materials and Electronic Devices of the Université catholique de Louvain, where he has been a full professor since 2007. He is author or co-author of more than 350 scientific articles.[/caption] Their advanced RF-SOI technology is now behind a wide range of applications and systems in areas including mobile devices, satellite communications, IoT, automotive radar and aerospace. If you want to better understand all this, a few years ago UCL and Soitec teams contributed an excellent article to ASN. It clearly explains how and why these new substrates came to be. You can still read it here. (Or if you're still a little confused about RF-SOI vs. RF on FD-SOI, here's a piece we did back in 2015 that explains the basics.)

China Mobile is the world's largest* telco. So when Danni Song, one of the company's high-level project managers presented at the SOI Consortium's 5th International RF-SOI Workshop in Shanghai, you can bet people listened. With each new slide, a glowing sea of cell phone cameras rose over the heads of the audience in the huge, packed ballroom. [caption id="attachment_11612" align="alignleft" width="300"] (Photo courtesy: SOI Consortium, Simgui)[/caption] Over the last month, there's been a lot more coverage of 5G in the press (especially after the recent Mobile World Congress (MWC) – check out Junko Yoshida's EETimes piece for example). For ASN readers who want to know more about 5G and RF-SOI in China, here's a reminder that Song's presentation, and many of the others given by leading companies at the RF-SOI Workshop last fall, are now posted on and freely available the Consortium website Events page. Click here for the listing and links.The theme of the workshop was IoT, mobile, 5G connectivity, and mmW. As Dr. Xi Wang, Director General of SIMIT/CAS (the Shanghai Institute of Microsystem Information Technology in the Chinese Academy of Sciences), said in his opening keynote, China is strong in RF-SOI. RF-SOI will be growing at a CAGR of over 15% for the next five years, and China has production, design, wafer manufacturing and good momentum. “We will make a great contribution to the whole IC industry,” he predicted.Of note, too, Russell Ellwanter, CEO of TowerJazz, gave what turned out to be a very inspirational keynote about Value Creation, and the importance of treating your suppliers with respect. He credits his company's close relationship with RF-SOI wafer-supplier Soitec for TJ's claim to the world's best linearity. Five of their seven fabs do RF-SOI. LNA (low-noise amplifers) are a big market driver, and with RF-SOI they can integrate the LNA with the switch.Here are some more highlights from the day – but by all means check out the presentations for details. (You can click on the illustrations to see them in full screen.)China MobileIn her presentation, Embrace a Brand New Cooperation in 5G Era, Song asked where RF-SOI could help in her wish list. Could it increase integration and decrease cost and power consumption? Can it help improve NB-IoT device performance? The supply chain needs to come back around into a circle, so that the telcos are connected to and get insights from the wafer substrate providers, she said. [caption id="attachment_11608" align="alignright" width="300"] (Courtesy: China Mobile, SOI Consortium)[/caption] China Mobile has a 5G Innovation Center, and has established test labs in 8 cities. And the government has announced a 5G launch in 2020, with pre-commercial trials now going into 20 cities. So she was at the RF-SOI Workshop as much to listen and learn as to share China Mobile's vision.Sony [caption id="attachment_11613" align="alignleft" width="300"] (Courtesy: SOI Consortium and Sony)[/caption] The presentation by Kidetoshi Kawasaki, GM of Sony Semiconductor Solutions, focused on antenna tuning, which he said is one of the fastest growing things in cell phones. Antenna Tuning Progress SOI Single Chip Integration for 4G/5G UE (note that UE = user equipment) looks at antenna aggregation, and why it is important for carrier aggregation (CA) and MIMO. Sony has developed an SOI-based next-gen process for 5G integrating passive components. That's why RF-SOI is important and will be continued to be used in the mobile market, he said.GlobalFoundriesGF has developed demo vehicles to help customers, said Sr. Director of the RF Business Unit, Peter Rabbeni. (Over the years they've shipped over 32 billion RF-SOI devices, btw.) In his presentation, RF-SOI: Delivering Performance Integration for the Next Generation of Mobile,he noted that RF is becoming more complex than digital. As a result there is a need to integrate to help reduce cost: this is a direct correlation to the standards that are driving complexity. At the same time, performance requirements are increasing, so the challenge is driving increased performance at the same or lower cost than previous generations of products. [caption id="attachment_11609" align="alignright" width="300"] (Courtesy: GlobalFoundries and SOI Consortium)[/caption] To meet 4G/LTE and 5G's evolving performance demands, GF has recently introduced two new RF-SOI platforms, which he detailed in the presentation. 8SW enables increased integration of front-end modules (FEMs), while 45RFSOI is for mmWave FEMs. (In a separate presentation, IDDO-IC CEO Denis Masliah presented a Differential Complementary Millimeter Wave Power Amplifier for 5G using 45RFSOI process, which is currently being fabbed by GF.)RF-SOI Wafer SuppliersThe two leading RF-SOI wafer suppliers, Soitec and partner Simgui, both gave excellent presentations. Though Soitec EVP Bernard Aspar's presentation Engineered Substrates as Foundation of Innovation in RF is not posted, he made some important points. Up til now, RF-SOI has mainly been about switches and tuners, he said, but there are other opportunities that offer the potential for huge growth. The full supply chain needs to be prepared, he said, and suppliers need to understand each other. Each technology requires the right substrate – and even as we move into sub-6GHz 5G, there is still work to be done in 4G. In fact Soitec is now offering services to help customers better understand new substrate options. [caption id="attachment_11611" align="alignright" width="300"] (Courtesy: Simgui, SOI Consortium)[/caption] Soitec's partner in China, Simgui, now uses Soitec's Smart CutTM technology for RF-SOI wafer production. Together the two are now producing over a million 200mm RF-SOI wafers/year, said Simgui Sr. Director, Kerui Wang. His presentation, RF-SOI – a Secured Substrate Supply Chain, looked at their strategic partnership with Soitec, wherein they use the same tools and processes to deliver the same products meeting the same specs.Fabs and FablessTwo leading fabless companies – RDA Microelectronics (which was acquired by Spreadtrum) and SmarterMicro also presented their RF-SOI activities. Although their ppts are not posted, here are a few highlights.Longtime ASN readers will recall that RDA has been shipping high-volume, RF-SOI based chips to Samsung and others for over five years. In the presentation, RF-SOI in Current and Future RFFE Solutions, Engineering AVP Joseph Jia said that over last two years alone they've released almost 50 RFFE (front end) chips on RF-SOI. They see RF-SOI as the right match for switches, tuners and NB-IoT because of the low-voltage and tunability advantages.SmarterMicro's CTO, Peter Li, sees RF-SOI as a cornerstone of 5G. In his presentation, Reconfigurable RFFE in 5G, he said the goal is smart systems on fewer dies to decrease size and cost.Jeff Zhu, assistant director at SMIC, presented SMIC, 0.13um RF-SOI Platform Updates. Mainland China's largest foundry has recently moved its RF-SOI process from 180 to 130um, and he walked us through some chip designs.Throughout the day, presenters noted that RF is a great opportunity for China to take a leadership position. As one panelist at the end of the day noted, RF depends more on expertise and talent than digital, which depends more on manpower.Nanjing: A China RF CapitalJust before the Shanghai events, there was a 2-day event sponsored by the City of Nanjing, co-organized by SOI Industry Consortium and the City of Nanjing. Over 200 participants attended the workshop and tutorials on SOI applications, SoC development and manufacturing, EDA IP ecosystem, as well as a design tutorial for More than Moore SOI ecosystem. Almost all of those presentations are now posted on the Consortium – click here to get them.Some of the participants in the SOI Consortium's delegation also had the opportunity to visit the enormous Nanjing Sofware Park. Nanjing, we learned, is often considered China's “RF capital”. The list of the world's major RF players working in partnership there is certainly an international who's who.So, lots of good RF-SOI/5G info on the SOI Consortium website – check it out!~ ~ ~*in terms of market value and subscribers.

In Tokyo, Shanghai, Moscow, London, Paris or New York – wherever you are in the world –Japanese vehicles passing by on the roadways are a common sight. Three big reasons are their high quality, reliability and engineering. But Japan’s automakers are also legendary for their industry breakthroughs. A few highlights: In 1981, Honda introduced the first commercially available map-based car navigation system. The carmaker’s Electro Gyro-Cator used a gyroscope to detect rotation and other movements of the car. In 1990, Mazda equipped its COSMO Eunos with the world’s first built-in GPS-navigation system. In 1997, Toyota launched the world’s first mass-produced hybrid car -- Prius. In 1997, Toyota unveiled the world’s first production laser adaptive cruise control on its Celsior. In 2009, Mitsubishi rolled out the world’s first mass-produced electric car – i-MiEV. Off the roadways and often unheralded, it is supply chain companies including Japanese semiconductor makers that were a key engine of these innovations as they continue their rich history of driving automotive advances. Here’s a closer look at some of the key players and why they matter.Who Makes Automotive Semiconductors?Unlike other semiconductors, automotive chips are manufactured not only by integrated device manufacturers (IDMs) but also by captive fabs and automotive components makers such as Toyota and Denso.Denso, headquartered in Aichi prefecture, started in 1949 as a spin-off of Toyota’s electric components unit. Since 2009, the company has been the world’s largest automotive components supplier. Because Denso’s chips are mostly consumed internally, the company’s manufacturing revenue is not publicly available, but analysts estimate Denso’s chip business exceeds 200 billion JPY or USD $1.9 billion.Denso manufactures semiconductor components at two locations. Its Kota plant in Aichi prefecture manufactures power and logic chips, and the company’s Iwate (Iwate prefecture) facility, acquired from Fujitsu in 2012, produces semiconductor wafers and sensors.Denso Fab (Photo: Denso)Denso is developing SiC wafers for its power chips and plans to manufacture SiC inverters by 2020. Recently, the company announced joint research on Ga2O3 for power devices with FLOSFIA, a tech startup spun off from Kyoto University. In 2017, Denso established a semiconductor IP design company, NSITEXE, in Tokyo to design semiconductor IP cores – the semiconductor components that are key to autonomous driving.Toyota has been manufacturing semiconductor chips at its Hirose Plant since 1989. The semiconductor fab design and manufacturing technologies originated at Toshiba and moved to Toyota under a technology transfer agreement signed in 1987. In the power semiconductor arena, Toyota is jointly developing SiC devices with Denso and Toyota Central Research and Development Labs.Other car and component makers like Honda, Nissan, Hitachi Automotive Systems, Aishin Seiki and Calsonic Kansei are also developing and designing semiconductor chips.Microcontroller Units Microcontrollers (MCUs) were first employed in automobiles in the late 1970s to electronically control engines for higher fuel efficiency. Today, up to 80 MCUs are typically used in a car for powertrain controls (engine, fuel management and fuel injection), body controls (seat, door, window, air conditioning and lighting), safety controls (brake, EPS, suspensions, air bags and anti-collision) and infotainment.In December 2015, the microcontroller unit (MCU) supply chain experienced a major consolidation with the nearly $12 billion acquisition of Freescale Semiconductor by NXP Semiconductors, catapulting NXP to the top of the MCU market. NXP and Freescale were ranked second and third in global market share, after Renesas Electronics, at the time. Renesas held 40 percent global market share before its Ibaraki fab suffered severe earthquake damage in 2011 and hemorrhaged share after the loss of production capacity. Renasas continues to recapture market share at a rapid clip, with a growth rate of 5.2 percent and 24.6 percent, respectively, in the first two quarters of 2017, and claims it still leads the global MCU market for automotive applications with 30 percent share (source: Diamond Online, August 2017).Renesas was established as a joint venture of Hitachi and Mitsubishi and later merged with NEC Electronics. Consequently, Resesas’s MCUs, designed with Hitachi’s SH MCU cores, recently began a gradual shift to Arm cores. Renasas MCUs designed at 40nm or less nodes have been manufactured at TSMC, a Taiwan foundry, since 2012.CMOS Image SensorsCMOS image sensors serve as eyes of cars, performing camera functions on-chip. Today, automobiles typically are fitted with about 10 CMOS image sensors, a number forecast to grow to almost 20 by 2020 (source: Monoist, 2016). The sensor was originally used as a backup monitor but deployments grew with the advent of Advanced Driver-Assistance Systems (ADAS). The CMOS image sensor market is estimated to reach $2.3 billion USD by 2021, according to IC Insights. Sony is the global CMOS image sensor market leader, and ON Semiconductor and OmniVision Technology are big players in this growing segment.In 2016, Denso started using Sony’s CMOS image sensors to detect pedestrians during night driving. Sony manufactures CMOS sensors at Kumamoto TEC and Nagasaki TEC on Kyusyu Island. In 2017, Sony acquired Toshiba’s Oita plant to increase the capacity to respond to the growing demand for backside illumination CMOS image sensors for higher resolution images at a low-light environments.Sony’s 7.42 megapixel CMOS image sensor for automotive cameras (Photo: Sony Corporation)Power DevicesPower semiconductors provide electrical control functions such as rectification, voltage regulation (boost/step-down), and DA/AD conversion. The automotive industry’s migration from fossil fuel vehicles to hybrid and electric vehicles is driving strong demand for power devices. The leading power device makers are competing to develop higher performance devices on new materials such as SiC and GaN.For the past five years, the Japan government has funded SiC power device research and development (R D) projects and, in 2016, the National Institute of Advanced Industrial Science and Technology (AIST) and Sumitomo Electric Industries built a 150mm SiC wafer line at AIST’s Super Clean Room Facility in Tsukuba, Ibaraki. The facility supports volume manufacturing, reliability testing and quality assurance.Rohm is driving the Japan SiC power device industry. Rohm manufactures SiC power devices on 75mm, 100mm and 150mm wafers. In 2009, Rohm acquired a German SiC wafer maker, SiCrystal, which started supplying 150mm wafers to Rohm in 2013. Rohm also acquired Renesas Electronics’s Shiga plant (200mm line) in 2016 to manufacture SiC power and other discrete devices.Fuji Electric manufactures various power products including SiC power devices. Fully 30 percent of its products ship to the automotive industry. In 2013, the company built a new SiC line in its Matsumoto plant that includes both wafer process and packaging facilities. Fuji Electric now develops high-performance SiC devices on the latest 150mm SiC wafer technology.Toyota and Denso round out the Japan SiC power device industry. Denso markets its 150mm SiC technology under the “REVOSIC” brand. In 2013, Toyota built a SiC R D facility at its Hirose plant for future SiC captive manufacturing.SiC power semiconductors to improve vehicle’s fuel efficiency by 10 percent (target) (Photo: Toyota Motor Corp.)