Location: Richardson, Texas

Modus Test, a leader in advanced test socket testing solutions and performance validation, and yieldWerx, a semiconductor data and yield analytics platform, today announced a strategic partnership to help close the gap between test hardware and yield intelligence. The collaboration combines Modus Test’s high-performance socket test technology with yieldWerx’s enterprise-scale yield management platform to provide manufacturers with direct visibility into the relationship between socket health and device performance.

The partnership addresses a long-standing disconnect between test execution and data analytics in high- volume manufacturing. Degraded, misaligned, or worn sockets can introduce false failures or escapes without clear root-cause identification. By integrating hardware performance data with yield analytics, manufacturers can better distinguish contact-related artifacts from true silicon failures.
Through this partnership, customers can now:
• Monitor and trend socket performance across testers, sites, and handlers
• Correlate device failures to specific sockets, test cells, or contact events
• Identify unnecessary device rejects caused by socket degradation
• Detect potential escapes where devices pass due to intermittent contact issues
• Optimize preventive maintenance cycles using data-driven insights

By integrating Modus Test equipment data with yieldWerx’s wafer-, lot-, and device-level analytics, manufacturers gain the ability to separate true device behavior from test interface variability, improving confidence in test outcomes and accelerating root-cause resolution.

About yieldWerx
yieldWerx provides a semiconductor yield management platform that enables manufacturers to collect, analyze, and act on production data across the manufacturing lifecycle. The platform consolidates data from wafer fabrication through final test, delivering visibility into product quality, process performance, and yield improvement opportunities.

About ModusTest
Modus Test, LLC was founded on the idea that there are creative ways to improve results by combining innovation with the best-known methods in test design and manufacturing. Providing innovative test solutions includes the MPT series of parametric tests, systems, and accessories. Modus Test has a global presence and the capability to support customers in all the IC development centers and high-volume manufacturing sites around the world. See for yourself how combining innovation with best-known methods can improve your results.

Statements from Leadership
“yieldWerx was built to unify disparate manufacturing data into actionable yield intelligence,” said Aftkhar Aslam, CEO of yieldWerx. “Valuable data exists across testers, handlers, sockets, MES systems, and inspection tools, but it often remains siloed. Our platform connects these domains into a unified analytical framework that enables faster, data-driven decisions that reduce costs.”

“This partnership represents an important step forward in bringing greater transparency and intelligence to semiconductor test,” said Jesse Ko, COO of Modus Test. “Modus Test’s high-performance socket validation solutions, combined with yieldWerx’s powerful analytics platform, create a closed-loop ecosystem where hardware performance and yield outcomes are fully correlated. Together, we are enabling a smarter, more adaptive test environment.”

For further information, please visit https://www.yieldWerx.com or https://www.ModusTest.org.

• Read more about Modus Test Partners with yieldWerx to Deliver Closed-Loop Socket to Silicon Correlation

Breker Verification Systems and Moores Lab AI Partner to Create First AI-Driven SoC Verification Solution
• Test Suite Synthesis, agentic AI integration will enable automated specification test generation across range of SoC designs on varied verification platforms
• AI-driven synthesis verification flow prototype to be demonstrated during DVCon U.S. in March
• Joint Breker, Moores Lab AI reception at DVCon U.S. Monday evening followed by AI in verification panel
SAN JOSE, CALIF.––February 26, 2026––Breker Verification Systems and Moores Lab AI today formalized a partnership to create the first AI-driven SoC verification flow integrating Breker’s Trek Test Suite Synthesis with Moores Lab agentic AI technology.

The solution leverages Breker’s vast experience in test generation for complex system design scenarios with the agentic AI VerifAgent™ product from Moores Lab AI. It seamlessly enables automated multicore, multitool, C or transaction level modeling (TLM) test generation for complex SoC scenarios from manually composed specifications.

The flow uses agentic AI to read a specification and generate appropriate scenario models for test synthesis that will produce combined C and SystemVerilog tests that can be run on simulation and emulation platforms targeting high-coverage SoC scenarios.

A prototype of the AI-driven verification flow will be demonstrated in Breker’s Booth (#203) and the Moores Lab AI Booth (#101) during DVCon U.S. March 2 through March 4 at the Hyatt Regency in Santa Clara.

“SoC verification requires highly complex scenario tests that find unpredictable corner cases across advanced, multi-core architectures,” says David Kelf, CEO of Breker Verification Systems. “The Moores Lab AI VerifAgent technology is an excellent complement to our proven Trek synthesis products that leverages our deep verification experience to drive the first AI SoC verification solution.”

“Breker has long been a pioneer in portable stimulus and system-level verification innovation,” notes Shelly Henry, CEO of Moores Lab AI. “Integrating VerifAgent with the Breker solutions creates a powerful synergy that enables engineering teams to verify increasingly complex silicon much faster and with greater confidence. We’re excited to partner with Breker to bring AI-driven transformation to SoC-level verification workflows.”

Combining Test Suite Synthesis with Agentic AI
Test Suite Synthesis generates high coverage tests efficiently for complex SoC-specific scenarios using various verification approaches, while agentic AI can accelerate the understanding of specifications to automatically derive verification plans and scenario models.

Combining the two can drive an automated verification solution that enables test generation for complex SoC scenarios from a manually composed specification that may be applied across a broad range of designs on varied verification platforms.

Availability
The AI-driven verification flow will be developed throughout 2026.

For more information, visit: http://www.breker.com or [email protected], or www.mooreslab.ai or [email protected].

Breker and Moores Lab AI at DVCon U.S.
In addition to the AI-driven verification flow prototype, Breker will exhibit and demonstrate its RISC-V CoreAssurance and SoCReady SystemVIP and Trek Test Suite Synthesis solutions at DVCon U.S. To arrange a demonstration or private meeting, send email to [email protected].

Moores Lab AI will showcase the VerifAgent product and discuss its product roadmap for agentic AI-driven silicon engineering at DVCon U.S. Email [email protected] to schedule an on-site meeting.

On Monday, March 2, Breker and Moores Lab AI will host an evening reception at DVCon in the Hyatt Regency Hotel Cypress room beginning at 6:30 p.m. and followed by a panel discussion on AI-driven SoC verification.

About Breker Verification Systems
Breker Verification Systems solves complex semiconductor challenges across the functional verification process from streamlining UVM-based testbench composition to execution for IP block verification, significantly enhancing SoC integration and firmware verification with automated solutions that provide test content portability and reuse. Breker’s solutions include a SystemVIP library of scenarios for RISC-V and Arm, core and SoC testing, coherency, security and other critical areas. Breker solutions easily layer into existing environments and operate across simulation, emulation, prototyping, and post-silicon execution platforms. Its Trek family is production-proven at leading semiconductor companies worldwide and enables design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easy verification knowledge reuse. As a leader in the development of the Accellera Portable Stimulus Standard (PSS), privately held Breker has a reputation for dramatically reducing verification schedules in advanced development environments. Case studies that feature Analog Devices, Broadcom, IBM and other companies leveraging Breker’s solutions are available on the Breker website.

Engage with Breker at:
Website: https://www.brekersystems.com/
LinkedIn: https://www.linkedin.com/company/breker-verification-systems/
X: @BrekerSystems

About Moores Lab AI
Moores Lab AI is building the next generation of AI tools for semiconductor design and verification. Its agentic AI platform transforms the chip development lifecycle by drastically reducing engineering time and cost, without changing existing flows, tools, or documentation. Moores Lab AI is headquartered in Austin, Texas, and proudly develops its products entirely in the United States.

For more information, visit www.mooreslab.ai or on social media:
LinkedIn: https://www.linkedin.com/company/mooreslabai/
X: @MooresLabAI

• Read more about Breker Verification Systems and Moores Lab AI Partner to Create First AI-Driven SoC Verification Solution

Phoenix, AZ – February 18, 2026 – Plasmatreat USA, Inc., a subsidiary of Plasmatreat GmbH and a global leader in atmospheric pressure plasma systems and equipment, will showcase advanced solutions for particle-free, contactless, chemical-free, and inline-compatible surface pretreatment for semiconductor and electronics manufacturing at the IMAPS Device Packaging Conference, March 2–5, 2026, in Phoenix, Arizona.

As semiconductor devices continue to shrink while power densities increase, manufacturers face growing demands for surfaces that are exceptionally clean, oxide-free, and highly wettable to ensure reliable hybrid and chiplet bonding as well as wafer-level packaging. At the same time, flux residues, epoxy contamination, and oxide layers must be removed without chemicals while meeting stringent cleanroom requirements and maintaining consistent cycle times.

To address these challenges, Plasmatreat will present expanded plasma technologies designed to deliver low-particle, potential-free, dry surface preparation that integrates directly into inline production. These solutions enable both selective, localized treatment and uniform activation across large areas, resulting in stable interfaces, improved yields, and sustainable manufacturing processes without VOCs or aggressive chemical media.

Plasma Nozzle Technologies for Semiconductor Manufacturing

At IMAPS, Plasmatreat will highlight nozzle solutions based on Openair-Plasma® technology that support hybrid bonding, wafer-level packaging, and advanced semiconductor assembly.

The PDW100 dielectric barrier discharge (DBD) nozzle is a flat atmospheric plasma solution with a treatment width of up to 100 mm, enabling uniform activation across large, sensitive substrates. The system removes organic residues and oxide layers without generating particles, supporting high process stability and repeatability.

The PFA10 plasma nozzle delivers low-particle, potential-free plasma treatment for highly precise, localized surface preparation. The nozzle effectively removes organic contaminants and oxides while activating metallic and polymer surfaces, creating optimal conditions for hybrid bonding and chiplet stacking.

“With the expansion of our plasma nozzle portfolio, we are enabling new levels of purity and process reliability in semiconductor manufacturing,” said Hardev Grewal, President and CEO of Plasmatreat North America. “The PFA10 and PDW100 provide uniform, contamination-free surface treatment that is essential for reliable electrical and mechanical connections, even in ISO Class 1 cleanroom environments.”

HydroPlasma® Enables Advanced Residue and Oxide Removal

In addition to the nozzle technologies, Plasmatreat highlights HydroPlasma®, an advanced cleaning process that combines the physical effects of Openair-Plasma with the chemical reactivity of ionized water molecules to remove stubborn organic and inorganic contamination.

During the HydroPlasma® process, water is introduced into the plasma and ionized, creating highly reactive species that break down contaminants in a manner similar to detergent cleaning — but without chemical agents. The process is delivered through a precision jet, enabling targeted, non-abrasive cleaning of sensitive semiconductor components.

HydroPlasma® is particularly effective for removing epoxy residues commonly left on metal surfaces after die attach, underfill, encapsulation, potting, and rework processes. It also removes naturally occurring metal oxides that can degrade adhesion, electrical performance, and downstream process yields. The result is oxide- and residue-free surfaces that improve bonding reliability and overall manufacturing consistency.

The technology provides efficient removal of organic and inorganic contamination, including heavy oil residues, while remaining environmentally friendly, VOC-free, and safe for use on metal, glass, and polymer surfaces.

Plasmatreat’s Openair-Plasma® technology platform provides dry, chemical-free, and fully inline-capable surface treatment. The process reliably removes organic contaminants, silicones, and electrostatic dust while increasing surface energy to greater than 72 mN/m, supporting downstream processes such as die bonding, wire bonding, and underfill applications. Surface treatment is completed within seconds, delivers highly consistent results, and utilizes cost-effective process gases including compressed air or nitrogen.

• Read more about Plasmatreat USA Highlights Advanced Plasma Nozzle and HydroPlasma® Cleaning Technologies for Semiconductor Packaging at IMAPS

• Read more about yieldWerx and iTest Partner to Deliver Seamless, Real-Time Semiconductor Test Analytics

• Read more about Ayar Labs and yieldWerx Partner to Streamline Photonics Test Data Analytics, Delivering Measurable Results in Just 30 Days

LOS ANGELES (Jan. 28, 2026) – EMASS, a Nanoveu subsidiary specializing in next-generation semiconductor technology, today announced the successful tape-out of its 16nm ECS-DoT system-on-chip (SoC). The device has entered fabrication at TSMC, marking the transition of EMASS’s next-generation ultra-low-power edge AI architecture from final design into production silicon.

The 16nm ECS-DoT represents a process-node and architectural scaling of EMASS’s proven 22nm ECS-DoT platform, increasing compute density, memory bandwidth and system integration while preserving the ultra-low-power design principles that define the ECS-DoT family. The move to 16nm enables higher logic density and tighter subsystem integration, supporting more complex always-on workloads within the same constrained power envelopes required at the extreme edge.

The current 22nm ECS-DoT SoC is EMASS’s commercially available platform and is actively being designed into customer products today, including applications across wearables, industrial sensors, asset tracking, smart infrastructure and other always-on edge use cases. This in-market traction provides a production-proven foundation for the 16nm ECS-DoT, enabling customers to scale existing designs to higher performance and integration without changing software workflows or system architecture.

By transitioning to 16nm, EMASS is able to expand on-chip SRAM capacity, integrate additional system-level functions and enhance AI and DSP acceleration without altering the underlying programming model or software toolchain. Wireless connectivity, dedicated AI accelerators and fine-grained power-management blocks are tightly coupled within a single SoC, reducing reliance on external components and enabling continuous, low-latency operation in battery-powered and energy-harvesting edge devices.

“Reaching tape-out confirms that our ultra-low-power edge AI approach scales cleanly to more advanced nodes,” shared Mark Goranson, CEO of EMASS. “The 16nm ECS-DoT is not just a faster or smaller device. It's proof that always-on intelligence can move into more demanding applications without breaking power, cost or system constraints.”

The 16nm ECS-DoT increases system capability while reducing external component dependency, allowing developers to build more intelligent edge devices with fewer tradeoffs. Key capabilities include:

Fully integrated BLE subsystem — Eliminates the need for external wireless ICs, reducing board area, bill-of-materials cost and design complexity.
Expanded on-chip memory — Supports larger AI models and higher-throughput workloads while minimizing off-chip memory access for improved efficiency.

Adaptive fine-grained power-management architecture — Optimizes energy use for always-on, battery-powered and energy-harvesting applications.

Dedicated object-detection accelerator — Offloads vision workloads to increase throughput and reduce inference latency for edge vision use cases.

Integrated floating-point unit (FP16/FP32) — Accelerates DSP and mixed-precision AI workflows while simplifying developer toolchains and code migration.

Despite the move to a 16nm process node, the ECS-DoT architecture maintains full software compatibility across generations. Developers can migrate applications between the 22nm and 16nm devices with minimal changes, preserving existing investments while unlocking additional performance and system headroom. This continuity allows customers to scale functionality and intelligence over time without redesigning platforms or toolchains, accelerating time-to-market for next-generation edge products.

The tape-out of the 16nm ECS-DoT further strengthens EMASS’s “Atoms-to-Apps” development philosophy, aligning application needs, algorithm design and silicon implementation into a cohesive system-level approach.

“Tape-out validates years of architectural decisions,” said Dr. Mohamed Sabry, founder and CTO of EMASS. “With the 16nm ECS-DoT now in fabrication, we’ve demonstrated that our architecture can deliver higher integration and capability without sacrificing energy efficiency. This milestone positions EMASS to support a broader range of always-on edge AI applications while staying true to the fundamentals that define our platform.”

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About EMASS
EMASS – a subsidiary of Nanoveu Ltd (ASX: NVU) – is an advanced semiconductor company specializing in ultra-low-power AI system-on-chip (SoC) solutions for edge computing. The company's flagship ECS-DoT chip delivers high-performance AI processing for vision, audio, and sensor data directly on-device, maximizing energy efficiency through its RISC-V architecture and non-volatile memory technologies. This always-on intelligence solution is optimized for power- and space-constrained applications including drones, wearables, healthcare devices and industrial IoT systems. For more information, visit nanoveu.com/emass.

About Nanoveu
Nanoveu is a listed company advancing human–machine experiences at the edge through a portfolio that spans ultra-low-power AI and glasses-free 3D technologies. Its subsidiary EMASS designs advanced system-on-chip (SoC) solutions that deliver efficient, scalable on-device AI for smart devices, IoT applications and 3D content transformation – enhancing Nanoveu’s reach across rapidly growing AI, edge computing and 3D content markets. EyeFly3D™ is Nanoveu’s end-to-end platform for glasses-free 3D, uniting proprietary screen technology with sophisticated content processing software and, now, EMASS’s ultra-low-power SoC to bring immersive 3D to a wide range of devices and industries. The Company also develops and markets an advanced range of self-disinfecting and hydrophobic films and coatings under the Nanoshield™ brand, designed for applications including large-scale CSP and photovoltaic solar installations. Together, Nanoveu’s businesses deliver practical innovation that makes devices smarter, environments safer and experiences more immersive.

Media Contact
Zach Hynoski
[email protected]
+1 (732) 581-6237

• Read more about EMASS Tapes Out 16nm ECS-DoT, Advancing Always-On Edge AI