Technology and Trends

A lot has happened in fifty years, particularly when it comes to the microelectronics industry. Founded in 1970 by a group of semiconductor industry pioneers who believed that co-opetition — instead of traditional competition—would produce a more vibrant emerging industry, SEMI was born as an industry association.It's fitting during this week’s 50th annual SEMICON West (July 20-23, 2020) — a virtual event for the first time — that SEMI Chief of Staff Bettina Weiss offers her perspectives on the evolution of SEMI from one of the best seats in the house: the 24 years that she has spent helping the association change and grow.Vetrano: You’ve enjoyed a long rich history with SEMI, and now serve as the association’s first chief of staff. What roles have you played at SEMI up to this point?Weiss: I cut my teeth at SEMI by joining SEMI Standards, first serving as standards coordinator at SEMI Europe from ’96-’97. Over the next 11 years, I held a variety of positions at SEMI Standards, culminating with director of international standards from 2003-2008. Given that experience, I have to admit that SEMI Standards are still near and dear to my heart.I moved on to several leadership positions in our former global photovoltaics/solar business through 2014, and toward the end of that stint, I assumed additional responsibilities, becoming vice president of business development. That’s where I dove headfirst into expanding SEMI into emerging regions, including Vietnam, India and Latin America. SEMI goes where members see (or want to better understand) new opportunities, especially in places that had ambitious plans for fabs for microelectronics, including semiconductors and MEMS.In 2018, I became SEMI chief of staff, reporting directly to our president and CEO Ajit Manocha.Vetrano: Now I hardly know where to start! Since I have to decide, what does it mean to be SEMI chief of staff?Weiss: As the first chief of staff, I’ve been able to shape the position, combining the support of critical efforts driven by Ajit with additional project management responsibilities like our Smart Mobility initiative.Working with experienced leaders in our industry, such as the Board of Industry Leaders (BIL), is one of the more rewarding parts of my role at SEMI. The BIL is a group of global executives tasked with advising SEMI on strategic planning, especially when it comes to future-looking initiatives like Smart Mobility, Smart MedTech, Smart Manufacturing, and Smart Data/AI.A lot of the other things I do are meant to support the whole SEMI organization, in partnership with other senior leaders such as Michael Ciesinski, vice president of technology communities, as we create business plans and examine new revenue models that will keep SEMI sustainable and viable for the future. This includes issues as varied as workforce development and diversity and inclusion, and the new digital platforms we use to engage with our members.Vetrano: How does SEMI Smart Mobility initiative exemplify the model of engaging end customers in vertical markets that are important to members?Weiss: When you look at the rapidly increasing number of chips and sensors in and around vehicles, Smart Mobility at its core brings together both the semiconductor/sensor and automotive/mobility supply chains for a more transparent dialogue about needs and wants along the entire supply chain. We are thrilled to count automotive OEMs Volkswagen and Audi as SEMI members. We also work with Tier 1 suppliers such as Continental and many others to promote the open exchange of ideas and foster collaboration among all stakeholders.Smart Mobility is a good example of how SEMI connects two worlds that are now interdependent for the mutual benefit of all players. Automotive companies and component suppliers want to better understand new technology capabilities that enable tomorrow’s infotainment, safety, security and communication protocols. And semiconductor, sensor and component companies see huge upside in supplying the equipment, materials, devices and subsystems that enable the future of mobility. Smart Mobility is a win-win, and the founding concept of our Global Automotive Advisory Council (GAAC).Vetrano: As we look to COVID-19, the single most important event to influence the microelectronics industry — and every other industry — why is SEMI membership more important now than ever?Weiss: Our industry is facing a triple whammy of challenges: a global pandemic, ongoing global trade tensions that impact interdependent supply chains, and a global economic crisis. All these challenges will require our members’ ingenuity, innovation and collective action to overcome them. But inherent in those challenges are tremendous opportunities, and I have no doubt that our members and the entire global electronics ecosystems will find ways to help everyone prosper and advance.COVID-19 has had a huge impact on our members. From the onset of the pandemic, we’ve provided our members with resources including best business practices, insights and data from industry experts to help them respond to a virus that has already changed so many things we took for granted before March. Additionally, SEMI has also advocated with governments around the world on behalf of the industry for essential business status and essential travel to sustain operations. Visit SEMI COVID-19 Resource page for information on industry best practices and much more.Vetrano: Before we look forward, what has changed dramatically in microelectronics since you started at SEMI?Weiss: Through my work with SEMI, I’ve witnessed dynamic, dramatic and sustained change in the microelectronics supply chain. Into the late 1990s, SEMI represented primarily semiconductor equipment and materials suppliers, and we worked with chipmakers – our members’ customers. That’s where a lot of important Standards work happened, for example, and the supplier-device maker relationship was pretty much our world. Over the years, we saw significant change in how companies partner and do business with one another. The digital transformation we’ve been witnessing for the past few years was the impetus for expanding our reach to bring companies in the extended electronics manufacturing and design supply chain together, from sand to system, so to speak. That was also when we invited associations representing flexible hybrid and printed electronics (FlexTech), MEMS and sensors (MSIG), and electronic system design (ESD Alliance) companies to join SEMI and our other technology communities for maximum cross-pollination. That’s because everything needs microelectronic devices and systems. Vetrano: Looking ahead now, what is can the microelectronics industry do to benefit humanity?Weiss: Semiconductors and sensors are often the unsung heroes of progress. Microelectronics can help bring prosperity to the billions of people now struggling on our planet. It can improve access to education for people through e-learning, it can advance agricultural production and streamline the food supply chain to help feed the world’s hungry, it can monitor the quality of the water we drink and the air we breathe, and it can get you in front of a doctor even in the most remote village in India.The beauty of microelectronics is that we are not gated by innovation. As the brilliant visionary Arthur C. Clarke once said, “The only way of discovering the limits of the possible is to venture a little way past them into the impossible.”As an industry association that helps technologists to venture beyond “the limits of the possible,” I invite like-minded technology adventurers to engage with SEMI, starting with registration to this week’s SEMICON West – our first virtual show.As chief of staff, Bettina Weiss reports to SEMI President and CEO Ajit Manocha and manages a broad portfolio of responsibilities. Major focus areas include advancing specific global strategic initiatives such as thought leadership (Think Tanks) and SEMI Smart Transportation vertical application platform, improving organizational efficiency, alignment and financial sustainability, acting as senior liaison to SEMI Board of Industry Leaders, leading strategic partnerships and M A activity, and supporting Manocha in creating a highly effective, agile global association.Maria Vetrano is a PR consultant at SEMI.

Innovations in the public sector are springboards for new products in digital health and personalized medicine. Since 2013, SEMI NBMC, funded by the Air Force Research Laboratory (AFRL), has been evaluating industry needs and soliciting proposals for new research into the foundations of device development and manufacturing of medically actionable devices.SEMI NBMC has run 17 separate programs with more than two dozen organizational participants developing materials, electronics, microfluidics, manufacturing processes and algorithms to create low-cost, wearable sensors. Most of these integrated sensing systems communicate wirelessly and incorporate high-performance silicon devices that are designed to move with the individual. Each of the projects was the result of a proposal received during NBMC’s annual proposal cycle. ​What’s Next in MedTech Device Development?We invite you to join the teams at SEMI, NBMC and AFRL to answer that question in a virtual series of sessions over the four weeks in August.For the past five years, NBMC has been conducting similar sessions for roadmapping the development of non-invasive human performance monitoring technology and manufacturing. The information feeds into the topics for upcoming RFPs, including the one we expect to release in September 2020. Previous Workshops (formerly entitled Blood Sweat and Tears) brought together industry and university innovators to explore current product research and provided excellent insights for the proposal evaluation teams. We believe the insights are also very useful to the business and technology planning direction for researchers and developers working on these products.Our focus is on early-adopting markets – medical professionals and their patients, Army and Air Force personnel and high-performance athletes.​ In this time of social-distancing and overall hesitancy to approach hospitals and medical offices, medical monitoring that provides medically-actionable intelligence is of even greater significance.But Doesn’t FitBitTM Have that Covered?Advancements are coming fast and furious – but medical professionals and insurance companies are struggling to distinguish innovations that provide actionable intelligence from those that provide generalized, non-actionable data.The workshop will focus on the medically relevant information that requires a great deal more accuracy, testing and certification before decisions are made. It is the innovations in this field that will lay the groundwork for new products in digital health and personalized medicine. Additionally, they are leading to advancements in aeromedical monitoring and diagnostics to support the U.S. Air Force’s mission to improve patient care during emergency air transport. The targeted future state is real-time monitoring of biochemical and physiological markers that can guide optimization of human performance and health. ​The SMART MedTech Virtual Workshop Series will link markets with manufacturing for medical relevancy – addressing both ends of the ecosystem. This forum will bring together the players across the growing range of industries that are entering or advancing human monitoring applications to:​ share competitive ideas that may be applied to product development​, assess roadblocks in bringing human monitoring products to market, and form partnerships that have become key in overcoming obstacles to successful manufacturing and product development. ​ Join the experts who are at the cutting edge of product design and manufacturing techniques. Indeed, the success of previous workshops was based on the unique membership of NBMC, where product and manufacturing-oriented engineers from industry, universities, and government labs form teams and pool resources (financial as well as technical) to accelerate human monitoring product development into manufacturing prototypes.Can’t Attend the Workshop?All sessions will be recorded and available for watching and re-watching on-demand. Join our interest list to receive regular updates on SEMI NBMC activities, including notification of the RFP expected to be available in October 2020.Find out more about the Smart MedTech Initiative and the NBMC Programs at our website.Rene Krantz is Director of R D Programs Business Development at SEMI. She is the primary manager of SEMI Smart MedTech Initiative and NBMC programs. Contact Rene at [email protected].

The COVID-19 pandemic has inflicted major impacts on manufacturing operations worldwide including in the semiconductor industry. The virus has left millions of people confined to their homes, resulting in a massive shift to virtual work and online engagement. In Singapore, where AEM is headquartered, our management team took proactive measures to protect our workers by implementing best practices ahead of the Singapore Circuit Breakers.AEM is globally deemed an essential service, requiring us to maintain operations and minimize impact to our customers. Business continuity plans that include work-from-home and safe-distancing guidelines are in place. As of the time of this writing, we are very fortunate that all of our employees are safe and that we’ve seen only minimal impacts to our customer commitments. AEM has confined this impact by spreading operational risks across our facilities in Asia, Europe, the U.S. and divisions in Singapore, Malaysia, China, North America, Central America, Finland, France and Vietnam. All told, these facilities employ more than 550 people (Figure 1).Figure 1 – AEM Global Presence As a global leader, AEM offers application-specific intelligent system-level test and handling solutions for semiconductor and electronics companies that serve the advanced computing, 5G communications and artificial intelligence (AI) markets.Leveraging our decade of experience, the latest AMPS solutions provide asynchronous, modular, massively parallel and smart system-level testing to meet the new test challenges of complex ICs. The modularity and scalability of these systems enables customers to scale their existing engineering device validation solutions into high-volume, massively parallel production solutions that increase faults coverage, reduces time to market, and decreases cost of test and ownership (Figure 2).Figure 2 – AMPS System-Level Test Solution In meeting 5G infrastructure test needs, AEM developed a field-deployable fiber optics tester. Called WideOptix SR4, the system was initially developed in collaboration with a world leader to support the 5G fiber infrastructure deployment in China and has now been adopted for some Ethernet standards testing. With our WideOptix SR4 development, we cultivated Silicon Photonics (SiPh) testing expertise that complements our AMPS system-level test capability. As part of our business continuation and risk diversifications plan, we had also set up factories in Penang (5,200m2) and Suzhou (3,600m2). Penang’s rising influence in the Southeast Asia semiconductor industry has prompted AMM (AEM Malaysia) to expand its scope to include value-added services with a Center of SSD Excellence and Center of Photonic Excellence.ASZ (AEM Suzhou) will continue to focus on the domestic market in China for further expansion and penetration with products ranging from cost-sensitive testers to state-of-the-art test measurement instruments. In Europe, AEM is focused on wafer-level test and cost-effective ATE test solutions. Finland-based AFORE specializes in MEMS and application-specific wafer testing with the ability to add physical stimulus. The company's state-of-the-art instruments enable the testing of devices such as diced IMU’s (Inertia and Motion Units) in continuous rotation on a wafer mounting ring. Our process increased test throughput by 3X compared to the traditional pick-and-place methods (Figure 3).Figure 3 – Wafer-Level Test Throughput Advantage A specialist in application-specific wafer handling, AFORE developed its latest design to support quantum computing in collaboration with its partner BLUE FORS. The company’s probing equipment features a handling solution with temperature tolerances to 2K (-270’C) to support cryogenic testing (Figure 4).Figure 4 – Cryogenic Quantum Computing Probing Solution AFORE also gained critical insights into creating total darkness, enabling us to further explore opportunities for dark matter testing. AFORE is currently in talks with a member of the LUX Photonics Consortium funded by the National Research Foundation (Singapore) to provide a dark body testing environment and handling for its IR detectors.In Europe, our acquisition of Mu-TEST in France helps diversify our product and service offerings while spreading our business continuity risks. Mu-TEST enjoys collective test-development experience of more than 320 man-years thanks to various ATE suppliers including Schlumberger and Credence. To help combat rising costs of traditional ATE, Mu-TEST developed cost-effective solutions using FPGA-based instruments supported by a full suite of test development, debug and production test software with links to EDA and standard interfaces. This provides Mu-TEST an agile platform that can be easily re-configured for different customer needs.This Mu-Test acquisition expands AEM’s system-level testing capability to include Functional Test, allowing BIST, SCAN, JTAG to test structural failures and perform other application-level test that interface directly with the DUT using the EVM (Electronics Validation) boards to increase fault coverage within the same test environment. Mu-TEST has also enabled AEM to form the recent partnership with UTAC to develop a cost-effective CIS test solution that addresses UTAC’s test needs and complements its CIS advanced packaging solutions. Our U.S. headquarters based in Chandler, Arizona has expanded its capabilities to provide application engineering.In summary, AEM has been expanding its global footprint while managing risk and has been fortunate to be positioned to manage the recent COVID-19 excursions. While each geographical location specializes in core technologies, all sites have access to one another’s manufacturing facilities in times of need and a pool of IP available to address new opportunities. We believe this risk diversification positions us well to serve the needs and interests of our customers worldwide.Lo Wee Tick is Director, Business Development, and Stuart Pearce is Senior Director, Field Marketing, at AEM Holdings Ltd.

As the COVID-19 quarantine-related restrictions for commerce and transportation are lifted in the Philippines, companies are dusting off desks, cleaning coffee mugs, warming up equipment and gradually bringing back staff to resume full operations. Of primary interest to manufacturing companies like Microchip Technology Philippines are the restrictions on the allowable workforce, the movement of personnel, transportation, and health and safety protocols affecting factory staffing, materials availability, and the ability to ship products. In the Philippines, these restrictions started to scale back in mid-May and are staged to continue in a series of continuing reductions every two weeks through the end of June. As business operations recover, challenges remain in managing the workforce, negotiating the supply chain and understanding the expenses required to operate under the “new norm” while Business Continuity Plans continue to be reviewed and revised.Here are some of the more important business-related elements of the quarantine levels enacted by the Philippines:Enhanced Community Quarantine (ECQ): In effect from March 17 through May 15, 2020, this was the initial lockdown with the strictest requirements, most notably requiring the general population to stay at home, imposing curfews, prohibiting all public gatherings including schools, halting public transportation and banning air travel while allowing cargo flights, skeletal workforces (~15%) for essential businesses (BPOs, IT and exporters, for example) and travel using some private vehicles with varying types of passes required to clear checkpoints.Modified Enhanced Community Quarantine (MECQ): In effect from May 16 through May 31, 2020, this was the first stage to ease control to allow up to 50% of employees to return to work at essential businesses. The easing also allowed gatherings of up to five people while maintaining most other restrictions.General Community Quarantine (GCQ): In effect from June 1 through June 15, 2020, essential businesses are allowed to resume full operations within health and safety protocols in place for physical distancing, disinfection and the wearing of Personal Protection equipment (PPE). Air travel is allowed to resume while public transportation remains restricted until June 21, 2020. Company shuttles are allowed for point-to-point services.Modified General Community Quarantine (MGCQ): Planned for June 16 through June 30, 2020, this is the transition phase to the “new normal,” which will continue easing the restrictions for contact-related businesses such as barbershops, salons, restaurants and the like. Movement and public transportation will remain restricted until June 22, at which point the last obstacle for businesses to fully resume operations will fall.While some larger companies during the most restrictive ECQ were able to house staff on site or nearby in skeletal crews, some smaller companies were unable to do so and may never recover from the loss in revenue or from the loss of employees. The majority of companies in the technoparks shut down under the ECQ and were rendered powerless to return workers to factories. For factories allowed to house employees on site, a huge effort was required to provide emergency transportation, accommodations, food and drinking water, toiletries, Wi-Fi, and even entertainment for the sequestered staff – all while maintaining health and safety protocols for physical distancing and disinfection. For example, Microchip Technology Philippines was able to build temporary sleeping cubicles and showers; to buy tents, foam mattresses, bedding and personal hygiene kits; to provide canteen and laundry services; and to allow Wi-Fi access for employees to stay connected to family and friends.Microchip Technology’s 11 Guiding Values help to define our corporate culture and guide our decision-making. One key Guiding Value on display as we’ve transitioned through the levels of quarantine due to the COVID-19 pandemic has been that Employees Are Our Greatest Strength. Exercising this Guiding Value has supported the expenses necessary to provide the safest, most comfortable living accommodations in the factory conference rooms, hallways, basement, and even in office cubicles.While many larger companies in the Philippines provide company shuttles at pre-established pick-up points, limited public transportation strands many workers at home with no way to reach to their assigned shuttle. To address this challenge, solutions including van brigades that can navigate narrow village streets to pick up workers should be considered though at an additional, unplanned expense. The physical distancing rules effectively halves the number of riders, which in turn requires a doubling of the shuttle buses, most of which are under lease. If shuttle bus leasing companies cannot provide more buses, employees who can work from home should continue to do so or drive to shuttle stops if they have personal vehicles. Leasing these additional shuttle buses was in no company’s budget as we began 2020.Additional measures under the new norm will be expensive – perhaps prohibitively so – for smaller companies that cannot afford to double the number of company transports due to physical spacing rules requiring them to halve workplace capacity, whose workplace environments cannot support physical distancing, and whose treasuries cannot afford to buy rapid test kits for employees and their families. If these smaller companies produce items critical to the supply chain, larger companies will feel the sting – and cease producing specific products during the qualification of an alternate supplier. Until the Bureau of Customs and staffing of third-party logistic providers is back to normal, and until ports are running at full force, materials and exports will continue to be delayed, potentially limiting the number of employees needed to return to work to run production.It has been very expensive for companies to survive through these levels of quarantine while keeping factories and employees in a state of readiness to return to work. Additional expenses will be borne for compliance to the new norm. As many businesses recover under the new norm, they’ll undoubtedly take a closer look at their business continuity planning, if any such plans exist, and if not, they should be created without hesitation.The problem with a typical business continuity plan is it tends to focus on one or a few concurrent major events – say, flooding or a power failure due to a typhoon – but it’s doubtful any plan took into account a global pandemic that affected so many factors simultaneously including workforces, supply chains, transportation, logistics and food supplies. As we return to work, we’ll have to adjust to the new workplace and embed the lessons learned during the COVID-19 pandemic into our business continuity plans. And, hopefully, we’ll never have to exercise those measures again.Greg Fisher is Managing Director at Microchip Technology Philippines.

By Sowmyan Rajagopalan, Founder and CTO, Thalia Design Automation FD-SOI is receiving significant traction with analog designers, but analog IP reuse often equates to tough choices. Porting chips from bulk to FD-SOI or creating new chips on FD-SOI means making decisions on porting existing bulk IP or starting from scratch. To invest the time and resources in reusing an analog IP requires a judgement call on the potential returns from the market and the time it takes to get the IP to that market to generate revenue is key – if a competitor's project hits the market first, then the potential returns are greatly diminished. There is also a need to understand the differences in process technologies and the impact those differences have on the efficient reuse of analog IPs. All this means that the demands on resources and time are high. Decisions, decisions A typical decision fork faced by many companies is whether to design new IPs, or if they should instead build a portfolio of analog IPs. Given the opportunity cost, availability of resources, time and resources needed for each option means that doing both is a difficult option. Both have their advantages; designing new IPs allows companies to branch out and address new sectors or markets. New IPs often demand higher revenues and engages in-house designers as the work, by its nature, is more innovative and challenging. On the other hand, building a portfolio of analog IPs allows companies to expand in an existing market, bringing stabilisation and strengthening revenues from existing product sectors. But why should you have to choose when there’s a third option? Have your cake and eat it It is difficult for a company to drive both options internally – not least because there’s a paucity of good analog designers in the market, and the opportunity cost is simply too high. However, the good news is that firms like Thalia have the specialist expertise and toolsets required build a portfolio of analog IP, saving time and investment while in-house designers focus on new IP design. Looking back Over the last 18 months, there has been a rapid uptake of FD-SOI process technologies. With production at foundries such as GlobalFoundries and Samsung now in full swing, more and more analog designers are reaping the benefits of FD-SOI. At Thalia we’ve been at the forefront of some of these changes, having worked with multiple customers on projects that use FD-SOI technology. [bctt tweet="More more analog designers are reaping the benefits of #FDSOI. At Thalia we’ve been at the forefront of some of these changes, having worked with multiple customers on projects that use FD-SOI technology. - @Thalia_IP_Reuse CTO " username="soiconsortium"] Driving the shift to FD-SOI [caption id="attachment_34410" align="alignright" width="347"] (Courtesy: STMicroelectronics)[/caption] This figure contrasts the structures of traditional bulk planar and SOI type transistors. The main difference is the inclusion of a buried oxide layer that isolates the channel of the transistor from the bulk silicon of the substrate. This results in a very thin, controllable channel structure, with much lower leakage currents being ‘lost’ into the device substrate than traditional alternatives. This in turn improves two key figures of merit for the device. First, standby power consumption is dramatically reduced. Second, the threshold voltage is much more predictable and controllable – yields are improved, and power/performance tradeoffs via voltage scaling are more easily enabled. The penalty is that FD-SOI transistors are generally not so fast. But one other feature of the technology – particularly important for mixed signal and analog designs – allows smart designers to mitigate this effect. Biasing the body structure at a different voltage to the source enables the designer to trade speed for power: a reverse bias increases the threshold voltage of the device, making it slower, but reducing leakage current; conversely, forward biasing reduces the threshold voltage, increasing the speed of the device, at the cost of power. Design migration Thalia has worked on a number of projects that utilize SOI technologies. A recent RF front end for Bluetooth Low Energy (BLE), for example, used exactly the techniques I have outlined above. We migrated an entire subsystem design, composed of around 30 blocks (including ADCs, PLLs, mixers, amplifiers and power controllers), to a 28nm Samsung FD-SOI process. [caption id="attachment_34412" align="alignright" width="451"] Click on this slide to see a YouTube video of the full Thalia presentation given at the Design Reuse FDSOI Virtual Event in March 2020.[/caption] The circuit was verified for compliance with design specifications. Design changes were implemented to ‘nudge’ the design to meet the requirements. And we made full use of the body biasing techniques I have already outlined. We used reverse body biasing to keep leakage as low as possible in parts of the circuit in which speed was not a factor; and, where speed was a key requirement, implemented forward gate biasing to increase performance. We’re expecting increasing numbers of customers to start moving their analog and mixed signal designs to SOI technologies in the coming months and years. The process is not without its challenges: but with an intimate knowledge of circuit design and optimization, and of the subtleties of the processes themselves, there are substantial advantages to be reaped. Technology analyzer – identifying the root cause when circuits fail A large part of the effort involved with migrating an IP from one technology to another is involved with qualifying the IP in the target technology; if a block doesn’t meet the requirements of the target technology, it won’t function. Identifying the cause of this – the technology characteristics that cause it – and then addressing them is key to a successful outcome. Whenever a key specification is not being met in the target technology, we have to determine which process technology or circuit characteristic is causing this. By using our automated technology analyser, we can take a design-centric approach to analyse and compare base and target technologies to see where the process technologies are similar and where they differ the most. The technology analyser considers both first and second order effects including FT, gm/id, Vdsats among others. Using this technology, we can identify which characteristics differ between the origin and target technologies. With traditional methods, identifying differences in characteristics would be time consuming, but our technology analyzer gives a clear and rapid identification of the issues, allowing us to fix any mis-matched topologies and achieve a functioning result in the target technology. The reality? IP reuse is not a dream or a myth Our platform comprises three elements – Technology, Methodology and Design Expertise. Using this trifecta, we have been able to deliver IPs in different technologies, nodes and with improved characteristics. The AMALIA technology consists of four elements: a technology analyzer, schematic porting, design enabler and layout migration. Tech analyzer: Using a design-centric approach, the platform addresses key first and second order effects of process technologies and extracts and compares characteristics between base and target technologies to provide the user with clear inputs on how similar the technologies are. Automated schematic porting: Taking the inputs from the analyzer and generates a circuit in the target technology. This circuit can then be verified for response and characteristics. Design enabler: Once the circuit design for the target technology is correct, the design enabler and our team of experienced designers can nudge the circuit back into specification. Layout migration: The final stage is focussed on putting together the base layout framework which is then expanding on by our experienced layout designers. Who we are?We are Thalia Design Automation. I founded Thalia in 2011, with the aim of improving the efficiency and process cost of analog circuit design and to rollout an analog IP reuse platform. We’ve worked with vendors, numerous foundries and different nodes and have design centres in Germany and India with our headquarters in the UK. We have successfully rolled out an analog IP reuse platform that combines smart technology, a smart methodology and our smart and experienced resources to streamline the IP reuse process. In doing all this, Thalia regularly provides customers with a time saving of around 50% compared to a traditional circuit redesign. And as I stated at the beginning of this article, achieving a faster time to market is key to maximizing revenues from any IP.

Semiconductor companies that begin revising their long-term strategies now may emerge stronger in the next normal.In the months after the coronavirus began to spread, semiconductor companies moved decisively to protect employees, secure supply chains, and address other pressing concerns. Although the situation is still serious and many governments are still imposing physical-distancing requirements, semiconductor leaders are now looking ahead to the time when the pandemic abates and the next normal begins. To prepare for that moment, they are thinking about strategies for reimagining and reforming their business models—two activities that McKinsey described in a framework for responding to the coronavirus.Every aspect of the business model could be subject to change, including the composition of product portfolios, capital expenditures (capex), R D strategy, demand forecasts, supply-chain footprints, production decisions, and options for mergers and acquisitions (M A). But with so much uncertainty ahead, semiconductor companies may have difficulty making strategic decisions. To move forward, they should first establish a solid baseline for their company (see sidebar, “Determining the starting point,” for more information on this topic). With this foundation, semiconductor companies can chart a path to the next normal by focusing on the following questions: What recovery scenarios are most likely, considering evolving demand, economic developments, and other global changes? What is the impact of the COVID-19 crisis on long-term trends and demand? How can we emerge even stronger from the crisis? In past downturns, companies that thought about strategic questions early in the crisis were most likely to recover quickly and become market leaders. Although the COVID-19 pandemic is unprecedented in modern times, the need for long-term planning still holds true.Developing recovery scenariosCOVID-19 has significantly altered the fundamentals of the sector, including customer behavior, business revenues, and numerous aspects of corporate operations. Many companies have unclear future prospects, and some may not survive the crisis. Multiple recovery scenarios are possible, depending on potential government interventions and other variables that are now difficult to predict.Earlier, we published an article about the short- to medium-term outlook for semiconductor demand. Our analysis was partly based on assumptions in two of the nine scenarios that McKinsey developed for the COVID-19 recovery, both of which assume that the spread of the coronavirus is eventually controlled and catastrophic economic damage is avoided. In the first scenario, termed A3, global gross domestic product (GDP) recovers in the fourth quarter of 2020; in the second, termed A1, recovery is delayed until late 2022. Since the original analysis, we have updated the estimates to include 2021 demand.Both recovery scenarios suggest most semiconductor segments will experience negative year-on-year revenue growth in 2020.Both recovery scenarios suggest that most semiconductor segments will experience negative year-on-year revenue growth in 2020. Looking ahead to 2021, however, we expect that the situation will improve as most end markets recover, mostly because the starting point for 2020 will be much lower than it was in previous years. In the more optimistic A3 scenario, only a few segments meet the growth expectations that were forecast before COVID-19 emerged by 2021 (Exhibit 1). In the more pessimistic A1 scenario, the number of segments that recover is even lower (Exhibit 2). Within the individual segments, a few trends stand out: PCs. This segment will see the sharpest drop in demand and the performance gap will become more serious over time. Most people will buy all the home-office electronics that they need for remote work in 2020, lowering demand for next year. Meanwhile, enterprises may continue to delay investments in PCs to control expenditures, even if the recovery is proceeding. Automotive. In the more optimistic recovery scenario, A3, the automotive segment sees year-on-year growth of 28 to 36 percent in 2021. This estimate is based on the assumption that governments will offer incentives to car buyers. In A1, the scenario with the delayed recovery, government incentives are not as strong and growth remains in the 1 to 5 percent range. Wired communication. Growth in this segment could exceed pre-COVID-19 forecasts in both 2020 and 2021. This is one of the few areas where a delayed recovery would actually contribute to higher growth than the more optimistic scenario, since continued remote work and homeschooling will stimulate demand for wired communication. Evaluating the impact of the COVID-19 crisis on long-term demandBeyond 2021, semiconductor companies may have more difficulty predicting demand because even greater uncertainty abounds about healthcare and business developments. As companies create long-term plans and evaluate potential scenarios, trends in two areas deserve particular attention.Market pullOver the past few months, people around the world have experimented with new ways of working, studying, and communicating through videoconferencing and other technologies. Such trends could have a lasting impact on semiconductor demand and open new possibilities for existing products and services. For example, demand could increase for semiconductors that enable servers, connectivity, and cloud usage as online collaboration grows. Semiconductors may also be in high demand for the following products and services: contactless solutions, including touch screens and elevator buttons ambient assisted-living devices, including sensors, that help elderly and chronically ill patients remain in their homes, rather than moving to facilities automated-delivery solutions for the last mile, such as robots and drones digital work processes and the Internet of Things, especially in lagging sectors, such as healthcare, government, and defense Of course, COVID-19 could also decrease semiconductor demand in several important areas. Some automotive makers have already begun to postpone investment in autonomous driving because their lower revenues meant that less funding is available for R D. In other areas, demand trends are difficult to predict. Looking again at mobility, it is clear that public transportation is now less popular because people fear viral transmission. If subway and bus ridership remains low, or if more people begin to purchase private cars, semiconductor demand could shift in response.Monitoring industry shifts and geopolitical responsesOn the supply side, the pandemic has exposed risks that were previously unrecognized, leading to potential shortages of critical parts and components. In response, many semiconductor companies are already reconfiguring their supply chains to improve resiliency, and the changes may continue into the next normal. As they plan ahead, semiconductor companies might want to create scenarios that show the potential impact of localizing production, increasing stock and inventory levels, or making other changes.Within plants, the COVID-19 crisis could accelerate automation and the adoption of Industry 4.0 technologies. Remote manufacturing, diagnostics, and maintenance could all become permanent features. If that occurs, semiconductor companies might become smart workspaces, with technologies that facilitate remote work for most employees. They might also encourage a hybrid model in which a certain number of employees are remote and the rest remain on site. The efficiencies gained through such changes, as well as their start-up costs, could influence future semiconductor revenues.Long-term scenario planning must also consider the geopolitical response to the COVID-19 crisis. To stimulate the local economy, several governments have already announced subsidies and incentives, but these often vary by region. China for example has announced extended state subsidies and tax breaks for consumers purchasing new electric vehicles, while the United States has reduced fuel-efficiency standards for automakers. Semiconductor companies should closely track such regional variations, since they may affect demand patterns, and note whether local government responses appear to be evolving.Emerging stronger from the crisisSemiconductor companies have developed effective crisis-management strategies during other difficult periods, including the dot-com bubble in 2000 and the Great Recession of 2008. But the COVID-19 crisis presents entirely new challenges that make it different from any previous downturn. It hit unexpectedly and has exacted an immense humanitarian toll in addition to causing economic hardship. Although no playbook exists for such a crisis, some lessons from past downturns may apply if semiconductor players want to emerge stronger in the next normal.Modestly reducing capital expendituresIntel’s cofounder, Gordon Moore, once observed, “You can’t save your way out of a recession.” Large capex reductions are unavoidable if companies need greater liquidity to survive a crisis. But for companies in a better financial position, experience suggests that enormous cuts may not be the best strategy. During the Great Recession, many of today’s leading companies reduced capex less than their competitors and thus were better positioned to prepare for growth once the economy began to recover. With the current crisis, companies that proceed with plans to create next-generation products, purchase equipment, or make similar investments will be prepared if demand surges as the economy recovers. Those that hold back may have difficulty catching up, since some improvements can take years.Focusing R D budgets on next-generation productsFor maintaining a strong R D strategy during a crisis, three actions can be critical: Limiting cuts to R D budgets. As with capex, research shows that top companies tend to make moderate R D cuts during a downturn, allowing them to sustain a rich and evolving product portfolio. Unless liquidity issues require more significant cuts, companies should strive to fund innovation, rather than setting the bare minimum budget needed to keep R D running. Those companies that retain their focus on R D innovation now could gain long-term advantage over competitors, given the often lengthy timelines for developing new products. In some cases, the lagging competitors may never close the innovation gap. Focusing on next-generation products. Although semiconductor customers might be limiting their spending now, demand for new and innovative products could surge once the economy begins to recover. Rather than simply improving products using current state-of-the art technology, companies should also invest in next-generation products using new technologies. They may not generate revenue from these products over the next 12 to 24 months, but they will be well positioned once customer demand surges. Keeping a close eye on trends. Forward-thinking semiconductor companies will try to determine what products will generate the highest demand post-COVID-19 and prioritize their R D investments accordingly. Their analysis should encompass all areas, from new manufacturing techniques that allow for smaller process sizes to more innovative sensors. To make the right decisions, semiconductor companies must closely monitor new trends and customer behavior. If unexpected market shifts occur, they may need to take a new course. Taking a strategic approach to mergers and acquisitionsSemiconductor companies may also emerge stronger from the COVID-19 crisis if they take a strategic, systematic approach to investment and divestment. A retrospective, cross-industry analysis of 1,000 businesses shows that today’s top 100 companies were 10 percent more likely to undertake programmatic M A—the regular pursuit of modestly sized deals—both during and after the Great Recession (Exhibit 3). For divestment, the top 100 companies also unloaded 1.5 times more assets than their peers during the downturn. Another striking finding: the top companies also were more likely to pursue smaller deals. Overall, their average deal value was about 9 percent lower than that of competitors.A programmatic approach to M A is well-suited to the current era, since governments may implement stricter controls on large deals to limit foreign investment. It is possible that some protections may even extend to smaller deals to protect local businesses from hostile takeovers by international companies, so semiconductor players must examine regional regulations closely before proceeding with any M A activity.The world will be a different place after the COVID-19 crisis, and we do not yet know the extent of the changes within business, healthcare, and society as a whole. With so much uncertainty ahead, semiconductor companies will benefit by creating multiple future scenarios, each showing different macroeconomic and virus-related outcomes, as they set their strategy for coming years. They should embrace the uncertainty as part of their operating model, since agility and the ability to adapt quickly will be far more important than sticking to a plan. As in previous downturns, those semiconductor companies that act quickly could emerge stronger. Modest capex cuts, a focus on R D innovation, and a programmatic approach to M A could help them capture growth and create leading-edge technologies that will be in high demand once the economy begins to recover.About the authorsHarald Bauer is a senior partner in McKinsey’s Frankfurt office, Ondrej Burkacky is a partner in the Munich office, Peter Kenevan is a senior partner in the Tokyo office, Abhijit Mahindroo is a partner in the Southern California office, and Mark Patel is a senior partner in the San Francisco office.The authors wish to thank Daniel Anger, Stefan Burghardt, Sungwoo Chung, Viktoria Medvedenko, Sebastian Peick, Klaus Pototzky, Larissa Rott, Luisa Russwurm-Bössinger, and Klaus Seywald for their contributions to this article.Republished with permission from McKinsey Company.

VeriSilicon provides platform-based, all-round, one-stop custom silicon services and semiconductor IP. For two years running, they’ve been the #1 Chinese IP provider and well into the Top 10 worldwide (per IPnest 2020). They’re also an FD-SOI design powerhouse. Founded in 2001, VeriSilicon first began work on FD-SOI in 2013. Now they’re headed for listing on the Shanghai STAR exchange. SOI News talked to President CEO Dr. Wayne Wei-Ming Dai about his company’s innovative business model, and opportunities for FD-SOI.SOI News (SN): You call the VeriSilicon business model “SiPaaS”, for Silicon Platform as a Service. Can you tell us what that means? Is it particularly well-suited to designs based on FD-SOI? Dr. Wayne Wei-Ming Dai (WD): We see SiPaaS as the third transformation in the semiconductor industry. If you take a minute to look at the evolution, first was the IDM model of the 1960’s and 70’s, largely based in the US and Japan and driven first by the US military, then home appliances and consumer electronics. The second transformation was the foundry model, driven heavily by the PC and cellular communication, with a geographic center heavily based in Taiwan and Korea. That solved the CAPEX challenge. Now with the IoT, we solve the OPEX – operational expenses – challenge. Although 60% of our business comes from outside China, we do see particularly good opportunities for China. With AI and AIoT, there’s a lot of custom designs. You have a new model with the chip as a system, with lots of IP – but it also is much more expensive. The VeriSilicon SiPaaS model covers everything from IP to final tape-out, delivers packaged and tested parts, and that accelerates time to market and saves money. If you consider the share of R D expenses as a percentage of chip revenue, for leading fabless companies, they can be 20-30%, and you need to have a gross margin of 50% and higher. But if your gross margin is 40% or below, you might out of business. The VeriSilicon model seeks to transform the design-heavy model, where designers use their own IP, to the next wave, which is design-lite. When you’ve got a design-lite model for A/IoT, you don’t need such a big team. This is the third transformation. You first saw this starting in a major way in Israel, where going to design-lite enabled fabless companies to move very quickly. But you still need IPs, and for those working under a traditional model, we have those. In SiPaaS, we offer IP platforms. Chip design is kind of like building a house. If you want, we can just give you the kitchen – so that’s some specific IP. But we can also give you the entire house. The IPs form the solutions. For each type of application, there are similar IPs that need to be integrated. Sets of IPs form subsystems for IoT, automotive, medical, wearables, audio, video, etc. There are no boundaries on the platforms, but each have typical elements. In this industrial transformation, and now especially for AIoT, you’ll need many more chips in many different places. We have a lot of IP that we created organically, but we also made some major acquisitions over the years. For example, 13 years ago we bought a Dallas based DSP division from LSI Logic. Our design-lite platform approach plays particularly well in FD-SOI, where designers want to maximize the advantages of the technology. Remember that much of the original IP for FD-SOI comes from ST or Samsung. When Samsung first licensed 28nm FD-SOI from ST, we got a whole set of 28nm FD-SOI IP from ST with modification rights. So we started to play with them. Then that IP went to Synopsys. We have modified, optimized and customized it for customers. And with GlobalFoundries’ 22nm FD-SOI, when the IP comes out, we're the first ones invited to test it. So we focus on those IPs. We do benchmarks on ARM and others. And we’ve designed our own IPs for RF and more. We’ve done the body biasing circuits and software control, so we support design methodologies. People often ask us to show them how good FD-SOI is. So we do a lot of benchmarking. At 28 bulk, we can do apple-to-apple comparisons. And 28 bulk or 22 FD-SOI, it’s the same team, so we can do those comparisons, so they can compare the two nodes. And we’re partnering with more 3rd party IP companies – including smaller players – providing FD-SOI IP, which is great. [bctt tweet="Our design-lite platform approach plays particularly well in #FDSOI, where designers want to maximize the advantages of the technology - @VeriSilicon CEO Wayne Dai #IoT #edgeAI #wearables" username="SOIConsortium"] SN: You have been a very vocal champion of FD-SOI. Why? WD: We’re not against FinFET – that a really big part of our business and we’re very advanced in it. We were the first to do a tape-out on Samsung’s 7nm UV FinFET test chip and are working on 5nm. While overall we tape out over 30-50 chips a year, we are foundry neutral. But we recognize that FinFETs are not for everything: there are some things that FD-SOI does much better. Integrating RF, for example – it’s not impossible but it’s not natural in FinFET. Yes, if you’ve got a big digital chip running at high speed most of time, FinFET is better. But if you’re running high speed some of time, say around 20%, especially integrating RF, FD-SOI is better. And back biasing is impossible in FinFET. In the end, we “walk on two legs”. SN: What do designers need to know about FD-SOI? WD: Body biasing can sound complicated, but the thing is, you don't play with each transistor. In theory, you can control each transistor with body bias, but in reality, you do it region by region. With body biasing, you can dynamically make different parts of the chip behave differently. This is key. Some parts are reverse biased. Some parts are forward biased. You play with this block by block, and kick it in as-needed by software after the chip comes back. So in IoT, for example, where it's very serious low power, you may want to shut down certain parts when you're not using them, while other parts always need to be on. If you choose one of our platforms, we’ve taken care of that. There may be parts you only need to bring up and run at high-speed for certain tasks. So body biasing gives you all sorts of controls. With FinFETs you can't do that, you can just play with voltage scaling. You can drive up the speed – the dynamic power – when needed with forward biasing. During that time, you're not really worrying about leakage power because when the task is done you can completely shut down those parts again. It also changes tape out. Typically designers do worst case. But you might not need to design for the worst case: you leave too much on the table. With body biasing, if you solve for typical, when the chip comes back, you can tune and make adjustments post-silicon. So you can do an aggressive tape-out, which is much more effective than starting off with a worst case. True, if you sign off worst case, your chip can always run very fast, but sometimes you don't need that. And in order to solve for worst-case, you put in a lot of buffers or whatever for timing closure, which is unnecessary effort. What's more, for different applications, the worst case can be different: some applications may need some higher speeds and sometimes less. If you solve for typical, then depending on the application you can software-tune the device. In the past, you never had that kind of thing. With body biasing in FD-SOI, you can solve for typical, so you can save a lot of area and a lot of design cycle in terms of timing closure, in terms of use of buffers. If silicon comes back, and it's missing something – say you need it to go a little faster – I’ve done body biasing, so I adjust the timing. Most times it's probably ok, it's good enough. Of course, some applications you need some combination of fast and slow, and you can leverage the body-biasing post silicon to change what's fast and what's slow on the fly. Like in wearables, power is very critical – some parts are always on, and some parts are sometimes on. For the parts that are always on, you need to reduce the leakage, and you do that with reverse body biasing. For other parts, you bring them up and you run as fast as you can for a short period of time – in this case leakage isn't as important because most of the time it's shut down. But dynamic power is important. High performance is important. For that part you need forward biasing. With different parts of the chip, you can play with different things. Before, you had to do this before tape-out, and sometimes had to do worst-case, which should never happen: you leave too much margin on the table, because after silicon you couldn’t do anything. But now with body biasing in FD-SOI, you have the capability – you don't need to do worst case – if needed you can always adjust. And for different applications in the chip, you might need a different kind of operating frequency, right? So you can create different chips from the same chip. With body biasing, you can always tune to whatever you want. If I’m short of something, I can do some body biasing bring up the speed. Now that's different from voltage scaling. You cannot dynamically achieve voltage scaling. You might have two voltages – one's high, one's low. But you cannot continuously change. In FD-SOI the same die maybe has different applications with different performance requirements, so we don't need to do worst case design. They can come up with different performance chips in the same silicon. SN: What do you see as the drivers? WD: IoT, AIoT and automotive. Also RF, mmWave and connectivity. And at the edge, where you need very low power. FinFET and FD-SOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI. There are a lot of applications in this category. In 12nm FD-SOI, you’ll reach almost the same performance as 7nm FinFET at 14nm cost. [bctt tweet="#FinFET #FDSOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI /@VeriSilicon CEO #edgecomputing" username="soiconsortium"] You’ve seen some stagnation of IoT at the 40/55nm process nodes because at those nodes the performance was not as good as expected. You needed two AA batteries. The value of the IoT data was not generated, collected or analyzed. What you need is AI at the edge to pre-process the raw data so you lower network capacity requirements. AI at the edge is a great opportunity for FD-SOI. SN: How do you see the role of the SOI Consortium? WD: We work with the consortium for these big forums; in particular VeriSilicon co-founded and has now co-sponsored the Shanghai FD-SOI Forum for seven years. They’re the most visible and high quality. The consortium knows the people that need to know each other. There are a lot of meetings during these events, and a lot of deals are sealed; one signature event is the river dinner cruise where “everyone is on the same boat”. ~ ~ ~ Related VeriSilicon press releases: VeriSilicon Releases Most Advanced FD-SOI Design IP Platform on GlobalFoundries 22FDX for Edge AI and IoT Applications (2019-10-24). The VeriSilicon 22FDX IP Platform includes over 30 low-power, low-leakage and high-density memory compiler IPs and various key mixed signal IPs. VeriSilicon provides a one-stop silicon design service to customers designing for AIoT with mature IPs to shorten custom design cycles and reduce their R D costs. FD-SOI Body-Bias technology allows the user to adjust device threshold even after silicon is manufactured: it can enable dynamic tuning between High-Performance and Low-Power, and enhance the design flexibility without extra cost. Advanced ATSC 3.0 Chip Launched for Mobile and Broadcast Applications (2019-01-08). The demodulator SoC was designed and developed by Saankhya Labs with ASIC turnkey design and manufacturing services from VeriSilicon, using Samsung Foundry’s state of the art 28FDS (its Fully Depleted SOI process technology), chosen for its unique low power capabilities offered by the back bias option. (See more in-depth coverage on this announcement from SOI News here.) VeriSilicon Announces Ultra Low Power BLE 5.0 RF IP based on GLOBALFOUNDRIES 22FDX FD-SOI Process for IoT Applications (2018-11-01). The IP includes a transceiver that is compliant with the BLE 5.0 specification and supports GFSK modulation and demodulation. The silicon measurement shows that the sensitivity can be tested up to -98dBm with less than 7mW power dissipation in typical conditions. It largely improves battery life for low power IoT applications. In addition, the RF transceiver saves 40% area compared to a similar implementation on 55nm bulk CMOS. Besides the RF transceiver, this IP integrates on-chip balun, TX/RX switch and 32K RC OSC driver to save the BOM. Moreover, high efficiency DC/DC and LDOs are also available for power management. “Wearable and IoT markets especially the wireless earplug market are growing rapidly, and it will surge through consumer use, hearing aids, personal care and other industrial applications.” said Dr. Wayne Dai, Founder, Chairman, President and CEO of VeriSilicon. “By taking advantage of integrated RF capabilities of FD-SOI, in particular GF’s 22FDX, our BLE 5.0 RF IP will significantly reduce the system cost and greatly boost the growth momentum of wearable products such as wireless earplugs.” GlobalFoundries and VeriSilicon to Enable Single-Chip Solution for Next-Gen IoT Networks (2017-07-13). The integrated solution leverages GF's 22FDX technology to decrease power, area, and cost for NB-IoT and LTE-M applications. VeriSilicon's Artificial Intelligence Engine Delivers Multi-Sensory Experiences in NXP's i.MX 8 Flagship Applications Processor. (2017-06-08).